Memory Layout engineer (DSOT)
Memory Layout engineer (DSOT)
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Job Description
Job Responsibilities:
Implement top quality of layout for memory which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones.
Layout implementation process: floor planning layout construction physical verification and memory compiler leafcell creation.
Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tapeout flow.
Requirements
Minimum Qualifications:
Bachelor s degree in Electrical/Electronic/Computer Engineering or equivalent
At least 5 years of direct experience in custom Memory layout implementation (SRAM/ROM/TCAM) in advanced finFET/GAA process nodes
Proficient in understanding DRM of advanced CMOS technologies and have a good understanding of deep submicron and DFM issues (e.g. WPE LOD effects etc.)
Strong knowledge in floorplanning techniques at different hierarchies with emphasis on power mesh planning critical block placement critical signal routing and topdown integration flow
Strong knowledge in executing and debugging various physical verification checks like DRC LVS ERC Antenna Density ESD LUP EM IR etc.
Proficient in Synopsys/Cadence layout editors
Ability in script programming ( Tcl Perl or Cshell) is a plus
Team player and effective in crossteam communication and time management
Employment Type
Full Time
