Senior DFT Engineer
Senior DFT Engineer
Posted on :
08-05-2025
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1 Vacancy
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Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
Work hard. Have fun. Make history.
We are seeking a seasoned and strategic Sr DFT Engineer to Lead endtoend DesignforTest (DFT) planning execution and silicon readiness for complex SoCs. This role demands deep technical expertise handson ownership and proven leadership in taking chips from design to volume production.
As a Senior DFT Engineer you will be both the technical owner and handson driver of the DFT strategy and execution across complex highperformance SoCs. This role requires deep technical expertise the ability to architect scalable and robust DFT solutions and the discipline to personally engage in implementation and debug. You will work alongside worldclass design validation and test teams to ensure firstpass silicon success and scalable production test readiness. Ideal for a seasoned leader this role combines strategic ownership with direct execution driving full lifecycle accountability from early DFT architecture planning to highvolume silicon bringup and yield ramp.
Key job responsibilities
Key job responsibilities
Lead development & implementation of DFT architecture including system level DFT for a full chip
Write and guide others in writing design flow and project documentation.
Own DFT planning milestone tracking and crossfunctional checklist reviews.
Oversee design insertion and verification of DFT logic and components into full SoC and subsystem RTL netlists.
Review and signoff SoC level DFT mode timing closure using static timing analysis
Drive the signoff on a generation of highquality test and debug patterns for high coverage on silicon
Keep informed on and introduce new technology into DesignforTest process as appropriate.
Education:
BS/BE or MS/ME in Electrical Engineering Computer Engineering or related field.
Experience:
15 years in SoC/ASIC DFT including 3 years Leading DFT.
Proven DFT experience leading multiple SoCs/ASICs (endtoend) from architecture to highvolume production.
DFT Architecture Expertise:
Proven capability in architecting and implementing DFT strategies at both subsystem and toplevel including:
Scan architecture compression and ATPG implementation for high fault coverage and test quality.
MBIST BISR and BIHR flows including advanced sharedbus memory BIST integration.
IEEE 1149.x (Boundary Scan) IEEE 1500 and IEEE 1687 (IJTAG) test architectures.
DFTAware STA closure including constraint generation and timing convergence strategies for shift and capture paths.
RTL and gatelevel debug including mismatch triage and simulation correlation.
Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation.
Tool Proficiency:
Deep handson experience with Tessent / Industry Std EDA tools including:
IJTAG ICL extraction and PDL modeling.
DFT logic insertion pattern generation and diagnostics.
Design Background:
Experience in writing verilog/system verilog RTL related to DFT logic design.
ATE Test Readiness:
Lead DFTtoATE handoff including:
Drive generation and signoff of highquality test and debug patterns to meet DFT coverage targets.
Pattern validation format conversion and debugging across wafer sort and final test.
Collaboration with PE/Test teams for silicon correlation and production test optimization yield improvements.
Silicon Debug:
Drive postsilicon validation failure triage and yield learning using SCAN diagnosis and MBIST repair signature analysis.
Automation Skills:
Ability to build and maintain scalable DFT automation flows using Python Tcl or Perl.
Collaboration:
Proven success driving crossfunctional teams involving RTL physical design validation PE and manufacturing.
Execution Excellence:
Known for being proactive detailoriented and independently accountable for tapeout and postsilicon success.
Leadership:
Led multisite/global DFT teams mentoring engineers and managing design reviews.
Drove designfortest planning in collaboration with customers or design services partners.
Technical Depth:
Strong understanding of DFTAware yield improvement and FA including DPPM reduction strategies.
Ability to correlate presilicon vs ATE pattern behavior and debug marginality/escape issues.
Exposure to DesignforDebug (DfD) features like trace buffers signature capture and observability enhancement.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process including support for the interview or onboarding process please visit for more information. If the country/region youre applying in isnt listed please contact your Recruiting Partner.
Work hard. Have fun. Make history.
We are seeking a seasoned and strategic Sr DFT Engineer to Lead endtoend DesignforTest (DFT) planning execution and silicon readiness for complex SoCs. This role demands deep technical expertise handson ownership and proven leadership in taking chips from design to volume production.
As a Senior DFT Engineer you will be both the technical owner and handson driver of the DFT strategy and execution across complex highperformance SoCs. This role requires deep technical expertise the ability to architect scalable and robust DFT solutions and the discipline to personally engage in implementation and debug. You will work alongside worldclass design validation and test teams to ensure firstpass silicon success and scalable production test readiness. Ideal for a seasoned leader this role combines strategic ownership with direct execution driving full lifecycle accountability from early DFT architecture planning to highvolume silicon bringup and yield ramp.
Key job responsibilities
Key job responsibilities
Lead development & implementation of DFT architecture including system level DFT for a full chip
Write and guide others in writing design flow and project documentation.
Own DFT planning milestone tracking and crossfunctional checklist reviews.
Oversee design insertion and verification of DFT logic and components into full SoC and subsystem RTL netlists.
Review and signoff SoC level DFT mode timing closure using static timing analysis
Drive the signoff on a generation of highquality test and debug patterns for high coverage on silicon
Keep informed on and introduce new technology into DesignforTest process as appropriate.
Education:
BS/BE or MS/ME in Electrical Engineering Computer Engineering or related field.
Experience:
15 years in SoC/ASIC DFT including 3 years Leading DFT.
Proven DFT experience leading multiple SoCs/ASICs (endtoend) from architecture to highvolume production.
DFT Architecture Expertise:
Proven capability in architecting and implementing DFT strategies at both subsystem and toplevel including:
Scan architecture compression and ATPG implementation for high fault coverage and test quality.
MBIST BISR and BIHR flows including advanced sharedbus memory BIST integration.
IEEE 1149.x (Boundary Scan) IEEE 1500 and IEEE 1687 (IJTAG) test architectures.
DFTAware STA closure including constraint generation and timing convergence strategies for shift and capture paths.
RTL and gatelevel debug including mismatch triage and simulation correlation.
Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation.
Tool Proficiency:
Deep handson experience with Tessent / Industry Std EDA tools including:
IJTAG ICL extraction and PDL modeling.
DFT logic insertion pattern generation and diagnostics.
Design Background:
Experience in writing verilog/system verilog RTL related to DFT logic design.
ATE Test Readiness:
Lead DFTtoATE handoff including:
Drive generation and signoff of highquality test and debug patterns to meet DFT coverage targets.
Pattern validation format conversion and debugging across wafer sort and final test.
Collaboration with PE/Test teams for silicon correlation and production test optimization yield improvements.
Silicon Debug:
Drive postsilicon validation failure triage and yield learning using SCAN diagnosis and MBIST repair signature analysis.
Automation Skills:
Ability to build and maintain scalable DFT automation flows using Python Tcl or Perl.
Collaboration:
Proven success driving crossfunctional teams involving RTL physical design validation PE and manufacturing.
Execution Excellence:
Known for being proactive detailoriented and independently accountable for tapeout and postsilicon success.
Leadership:
Led multisite/global DFT teams mentoring engineers and managing design reviews.
Drove designfortest planning in collaboration with customers or design services partners.
Technical Depth:
Strong understanding of DFTAware yield improvement and FA including DPPM reduction strategies.
Ability to correlate presilicon vs ATE pattern behavior and debug marginality/escape issues.
Exposure to DesignforDebug (DfD) features like trace buffers signature capture and observability enhancement.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process including support for the interview or onboarding process please visit for more information. If the country/region youre applying in isnt listed please contact your Recruiting Partner.
Required Experience:
Senior IC
Employment Type
Full-Time
Key Skills
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