CADEDA Silicon DesignVerification Infrastructure
CADEDA Silicon DesignVerification Infrastructure
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Job Description
Role: CAD/EDA Silicon Design/Verification Infrastructure
Location: San Francisco CA / Seattle WA / Santa Clara CA
Job Type: Contract
Interview Mode: Phone/Skype
Job Description:
Seeking an experienced CAD/EDA Engineer for Silicon Design/Verification Infrastructure. Must have 5 years in EDA/CAD SoC/IP design System Verilog/UVM ARM/RISC NOC Python 3.x) Linux (Shell scripting Makefile) C programming SoC verification debugging and crossfunctional collaboration.
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Contract
Employment Type
Contract
