Formal Verification Engineer
Formal Verification Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Responsibilities:
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Serve as a technical leader in Formal Verification across IP subsystem and SoC levels.
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Develop implement and promote bestinclass Formal Verification methodologies driving adoption across both block and toplevel verification teams.
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Collaborate closely with architecture and design teams to derive formal specifications and integrate them into the design and verification process.
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Define and manage the scope of formal verification activities including environment creation coverage closure and deployment of advanced formal techniques.
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Build scalable and reusable formal verification environments to enhance efficiency and maintainability.
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Evaluate adopt and integrate EDA tools and solutions that support advanced Formal Verification capabilities.
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Provide mentorship and technical training to engineering teams on formal tools techniques and methodology best practices.
Minimum Qualifications:
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Bachelors degree in Computer Science Computer Engineering Electrical Engineering or a related field or equivalent practical experience.
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5 years of handson experience in Formal Verification.
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Indepth experience with formal verification techniques such as datapath verification sequential equivalence checking Xpropagation analysis clock gating and connectivity validation.
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Strong grasp of complexity reduction and abstraction strategies in Formal Verification.
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Demonstrated analytical problemsolving skills particularly in addressing complex design challenges.
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Proven ability to work collaboratively with crossfunctional teams including architecture design and verification.
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Proficiency in hardware description and assertion languages (SystemVerilog SVA).
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Solid scripting skills using Python Perl or Tcl.
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Handson experience with leading formal verification tools such as Cadence JasperGold or Synopsys VC Formal.
Preferred Qualifications:
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Ability to quickly interpret specifications and derive meaningful formal properties and behaviors.
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Experience verifying complex computeintensive blocks (DSP CPU GPU or custom accelerators) using formal methods.
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Background in verifying clock domain crossings lowpower designs and IPXACTbased register files using formal techniques.
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Experience working on largescale SoC projects and driving formal signoff at scale.
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Familiarity with endtoend flow automation from specification to formal closure.
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Experience using simulators and waveform analysis tools for debug and validation.
Employment Type
Full Time
