Staff Engineer Analog Layout
Staff Engineer Analog Layout
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Salary Not Disclosed
1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Marvell is seeking a Staff Analog Custom Layout Engineer to contribute to the development of highspeed connectivity broadband analog and data transport products.What You Can Expect
- Design and optimize analog mixedsignal layouts such as highspeed ADCs PLLs bandgap voltage references LDOs highspeed I/O circuits general I/Os and ESD structures in deep submicron CMOS technologies using Cadence or Synopsys tools
- Collaborate closely with circuit designers and other teams to meet project specifications and timelines
- Responsible for floor planning custom layout and verifying compliance with design rules and schematics including DRC LVS ANT LUP ESD and PERC
- Maintain detailed documentation of layout methodologies design decisions and verification results
What Were Looking For
Bachelors degree in Computer Science Electrical Engineering or related fields with 35 years of relevant professional experience.
Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 23 years of experience is preferred.
Experience in analog/mixedsignal layout design for deep submicron CMOS circuits.
Familiarity with advanced process technologies and FinFET is a plus.
Proficient in block level floor planning and capable of driving the project through in chip level floor planning a plus.
Experience implementing analog layouts to achieve tight matching low noise and low power consumption. Layouts may include analog blocks such as highspeed digital highspeed ADCs PLLs bandgap voltage references LDOs I/O circuits general I/Os and ESD structures.
Understanding techniques to manage IR drop RC delay electromigration selfheating and crosstalk
Experience with full chip layout and verification
Proficiency with CAD tools such as Cadence Virtuoso Mentor Graphics Calibre or Synopsys Custom Compiler.
Strong proficiency in interpreting DRC ERC LVS LUP and PERC reports
Ability to work independently with strong analytical skills creative thinking and selfmotivation
Ability to work across teams
Strong communication skills
Expected Base Pay Range (USD)
$ per annumThe successful candidates starting base pay will be determined based on jobrelated skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a yearend shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LIVM1Required Experience:
Staff IC
Employment Type
Full-Time
