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Design Verification Engineer
Location : Remote
Semiconductor Industry
Good DV Skill with major GLS work experience.
Expertise in testbench updates for GLS
Expertise in Scripting languages perl or python
Experience with Make Yaml & Json file systems.
Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).
Good understanding of RTL synthesis Static Timing Analysis & LEC Flows.
Experience with flow optimizations such as Grey/Blackboxing techniques
Good at communicating requirements/issues with Implementation PnR and Design teams.
Working knowledge of Confluence documentation version system GIT and Project with JIRA.
Please reply me with your updated resume and required details:
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Best Regards
Salman Shaikh
Full Time