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You will be updated with latest job alerts via emailProficient in Developing STA and EMIR solutions at FullChip at Block Level.
1 Hierarchical STA Flows
2 Top Block Constraint validation and budgeting
3 Full chip clock propagation
4 ETM and power view model generation and validation
5 Timing and Power Signoff checks to ensure final tapeout quality
6 PVT Corner selection and margining for Global/Local/Library/Process/Design variations to ensure silicon success
7 Proficient in scripting for such checks and developing flows for other members to use.
8 Build regression suite to validate versions and features
Required Experience:
Staff IC
Full-Time