Senior Principal Design Engineer - DFT

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Advantage

Cadence offers the opportunity to work on cuttingedge technology in an environment that encourages you to be creative innovative and to make an impact. Cadences employeefriendly policies focus on the physical and mental wellbeing of employees career development providing opportunities for learning and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. Additionally you get to work with a diverse team of passionate dedicated and talented individuals who go above and beyond for our customers our communities and each otherevery day.

Key Responsibilities

The Senior Principal Design Engineer will define the DFT Architecture for the next generation SoCs. This person will also be responsible for the implementation & verification including Scan PMBIST JTAG and other DFTs related logic. Additionally they will define and develop methodology for DFT insertion pattern development manufacturing tests verifications etc. They will work closely with cross functional teams to develop and verify DFTs structures and constraints as well as perform RTL and gate level (notiming and timing) simulations to verify DFT functionality. Finally they will work closely with Test Engineering for test program development and Silicon bring up diagnosis Yield improvement etc. and work closely with EDA RnD teams to propose and implement new features.

Requirements:

• BS in Electrical Engineering Computer Engineering or Computer Science with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• At least 8 years of relevant handson experience in Design for Test (DFT).
• Clear understanding of key DFT concepts like Scan compression Scan Stitching fault models (stuckat delay tests IDDQ Small Delay etc. IEEE P1500 MBIST IEEE 1149.1/6 (Boundary scan) IEEE 1687 etc.
• Working knowledge of RTL coding in Verilog Synthesis & STA
• Experience in at least one scripting language like PERL Python TCL or Shell is preferred.
• Selfmotivated team player with strong problemsolving skills to collaborate with various teams to achieve desired goals.
• Excellent written and verbal communication skills.

The annual salary range for California is $154000 to $286000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

Were doing work that matters. Help us solve what others cant.