Full Chip Floor Planning
Key Responsibilities
- Develop and execute fullchip floor plan strategies.
- Collaborate with design teams to define chip architecture.
- Ensure proper placement of functional blocks based on area power and performance constraints.
- Perform timing analysis to meet synchronization requirements.
- Conduct floor plan synthesis and optimization for highdensity designs.
- Integrate design for test (DFT) methodologies into floor plans.
- Utilize layout tools for physical design verification.
- Communicate effectively with stakeholders to resolve design issues.
- Prepare and present floor plan reports and documentation.
- Analyze and address signal integrity and thermal issues.
- Participate in design reviews and provide input for improvement.
- Manage and mitigate risks associated with design constraints.
- Assist in the evaluation and selection of design tools and technologies.
- Use advanced algorithms for optimization of chip layout.
- Follow industry best practices and stay updated on new methodologies.
Required Qualifications
- Bachelors or Masters degree in Electrical Engineering Computer Engineering or related fields.
- Proven experience in IC/ SoC floor planning and chip design.
- Strong expertise in EDA tools such as Cadence Synopsys or similar.
- Deep understanding of semiconductor physics and technology.
- Experience with RTL design languages like Verilog or VHDL.
- Solid grasp of physical design methodologies and constraints.
- Minimum 29 years of relevant industry experience.
- Experience with power budget estimation and management.
- Familiarity with standard cell libraries and FPGA architectures.
- Knowledge of DFT techniques and methodologies.
- Excellent communication and teamwork skills.
physical design,design tools,rtl design,dft techniques,signal integrity analysis,soc,full-chip floor planning,rtl design (verilog, vhdl),eda tools (cadence, synopsys),rtl coding