DFT Scan insertion Engineer ATPG
DFT Scan insertion Engineer ATPG
Posted on :
18-04-2025
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1 Vacancy
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Job Description
Job Title: DFT Scan Insertion Engineer (ATPG)
Location: Bangalore India
Experience: 36 Years
Responsibilities:
- Perform scan chain insertion in digital designs to enable structural test coverage.
- Implement and optimize ATPG (Automatic Test Pattern Generation) for digital circuits including logic and scan tests.
- Integrate DFT (Design for Test) methodologies into the design process ensuring test coverage and efficiency.
- Work with design and verification teams to review testability requirements and ensure proper test insertion strategies.
- Generate test vectors and analyze ATPG results to improve test coverage and design quality.
- Provide detailed failure analysis and debug of test failures working closely with the design and validation teams.
- Optimize scan insertion and ATPG flows to meet product and performance requirements.
- Collaborate with hardware and design teams to identify potential test issues early in the design cycle.
- Maintain and update DFT and ATPG tools and methodologies to ensure they are uptodate with industry standards.
- Perform static and dynamic test coverage analysis and provide feedback for improvements.
- Contribute to Design for Manufacturing (DFM) and Design for Reliability (DFR) efforts related to testability.
Required Skills & Qualifications:
- Bachelor s/Master s degree in Electronics Engineering Electrical Engineering or a related field.
- 36 years of handson experience in DFT Scan Insertion ATPG or related roles in semiconductor or digital circuit design.
- Proficiency in scan chain insertion techniques and methodologies.
- Experience with ATPG tools (e.g. Mentor Graphics Tessent Synopsys DFT Compiler Cadence Modus) for scan and ATPG pattern generation.
- Indepth knowledge of DFT methodologies and standards such as scan design BIST boundary scan and MBIST.
- Strong understanding of fault models (stuckat transition path delay etc. and test coverage metrics.
- Familiarity with HDL (VHDL Verilog) and scripting languages (e.g. Tcl Perl Python) for automation of test flows.
- Experience with physical design and layout constraints in relation to DFT and test insertion.
Preferred Skills:
- Knowledge of scan compression and test pattern compaction techniques to reduce test time and improve efficiency.
- Familiarity with SOC (SystemonChip) design and complex ASICs/FPGAs.
- Experience with Design for Manufacturing (DFM) and Design for Reliability (DFR) concepts.
- Experience in testability analysis including fault simulation and coverage analysis.
dft methodologies,scan chain insertion techniques,physical design and layout constraints,test coverage metrics,atpg,fault models,physical design,atpg flow,dft,hdl (vhdl, verilog),atpg tools,scripting languages (tcl, perl, python),dft scan insertion,hdl designer,scan insertion,automatic test pattern generation (atpg)
Employment Type
Full Time
Key Skills
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