ASIC Design Engineer
ASIC Design Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Key job responsibilities
Gate Level Simulation: Develop and maintain comprehensive gatelevel simulation test plans for verifying ASIC functionality and timing. Analyze simulation results identify and debug logic errors and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
Facilitate seamless integration across Firmware RTL Platform Software and Platform Drivers.
Develop Debug tools: RTL Emulation silicon bringup and functional validation.
Export Control Requirement:
Due to applicable export control laws and regulations candidates must be a U.S. citizen or national U.S. permanent resident (i.e. current Green Card holder) or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
Work closely with the system architects to develop worldclass SOC and IP blocks which meet power area and performance targets.
Define configure and integration SoC Subsystems
Contribute to the SoC floor planning effort
Define and develop any necessary support logic
Configure instantiate and integrate 3rd party IP blocks
Understand low power design & the impact of DFT on the blocks
Perform initial synthesis & timing analysis
Assist verification team in unit verification including test plan development
Assist with debug and bringup
5 years of noninternship professional software development experience
5 years of programming with at least one software programming language experience
5 years of leading design or architecture (design patterns reliability and scaling) of new and existing systems experience
5 years of digital design experience preferably in SoC design and implementation
3 years of full software development life cycle including coding standards code reviews source control management build processes testing and operations experience
Masters degree in computer science or equivalent
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Employment Type
Full-Time
