Senior Principal Engineer - SoC Verification
Senior Principal Engineer - SoC Verification
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Job Description
Job Summary:
The Verification role will involve many aspects of Functional Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level. A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A zerodefect mindset is a key enabler. Responsibilities encompass the development of verification test bench development of verification components test case development for simulation formal verification and emulation debugging failures and creating simulation cases for various studies.
Expectations include:
- Team leadership with technical guidance and tracking and Verification planning;
- Verification test bench development tuning and implementation.
- Development of verification test bench components such as drivers monitors response checkers as well as use most advanced UVM VIPs.
- Development of direct and constrainedrandom stimulus using c SV. Understands and analyzes RTL code functional assertion coverage results.
- Understands Develop functional coverage. Understands and develops system Verilog assertions.
- Understands and implements formal verification methods; Strong skills in debug failure recreation and root cause analysis.
- Applicant should have efficient debugging and logic skills.
Job Qualifications:
- C and UVM/SV based Test environment and Understanding of the design/architecture and ability to debug RTL/Gate netlist is MUST
- Coverage driven Verification for addressing Functional Performance requirement of the SoC regression management
- Microcontroller architecture ARM Cores Interconnect (NIC FlexNoC) Cache Coherency and Bus Protocols like AHB/AMBAAXI ACE
Following skills will have additional value:
- Memory controllers (Flash SRAMDDR3/4/LPDDR)
- Protocols like PCIe MIPI GPU (Graphics processing) Ethernet Serial / Quad flash
- Formal verification methodologies and Apps AVIP PinMuxing Verification Randomization
- Low Power intent verification using UPF o Exposure to pre silicon validation/emulation (Veloce Zebu)/FPGA Prototyping would be a plus.
#LIDNI
#LI2734Required Experience:
Staff IC
Employment Type
Full-Time
