Staff Physical Design Engineer
Staff Physical Design Engineer
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Job Description
Staff Physical Design Engineer
Our client is a leader in nextgeneration digital connectivity enabling highperformance data communication across the most demanding industriesranging from AI and the metaverse to data centers 5G infrastructure and autonomous vehicles. They deliver missioncritical IP through innovative engineering and a proven track record.
As a Staff Physical Design Engineer youll take ownership of implementing optimizing and verifying complex digital designs at the physical level. Youll work alongside frontend designers DFT engineers and verification teams to ensure the delivery of highquality silicon. This role focuses on advancednode physical implementationfloor planning PnR CTS timing closure and signoff verification.
What Youll Do
Drive all stages of physical design including floor planning placement CTS routing and optimization for highspeed digital blocks.
Own timing closure strategies including skew balancing delay optimization and ECO implementation.
Perform signal/power integrity analysis including IR drop and electromigration.
Apply OPC litho shrink methodologies at advanced nodes such as TSMC N4P.
Optimize designs for area and power using MultiVt clock gating and poweraware synthesis.
Conduct physical verification (LVS DRC DFM) to meet foundry signoff requirements.
Collaborate across design DFT verification and process teams to resolve implementation or manufacturability issues.
Build and maintain automation scripts (TCL Python Perl) to streamline flows and improve efficiency.
What Youll Need
5 years of experience in physical design for digital ASICs.
Handson experience with advanced nodes (TSMC N5/N4P/N3 or similar).
Proficiency with industrystandard EDA tools: Synopsys ICC2 Cadence Innovus Calibre PrimeTime RedHawk etc.
Deep understanding of PnR CTS STA IR/EM analysis and power optimization techniques.
Experience with OPC shrink flows and advanced node methodologies.
Familiarity with DFT techniques such as scan insertion ATPG or BIST is a plus.
Experience with multipatterning (LELE SAQP) and full signoff verification (DRC LVS DFM EM/IR PEX).
Strong scripting capabilities in TCL Python or Perl.
Analytical mindset with a datadriven approach to debugging and problemsolving.
Preferred: Direct experience with FinFET technologies such as TSMC N5/N4/N4P/N3.
Please reach out to with your resume if youre a fit for the position and interested in learning more.Required Experience:
Staff IC
Employment Type
Full-Time
