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You will be updated with latest job alerts via emailSenior Design Verification Engineer
Our client is a key player in advancing digital technology by accelerating highperformance data communicationfrom AI and the metaverse to seamless video and beyond. Their technology is foundational to innovation across dataheavy industries such as data centers AI networking storage 5G and autonomous vehicles. Known for their cuttingedge solutions and reliable they help shape the future of digital systems.
The Digital Design Verification team fosters a collaborative growthoriented culture where engineers are encouraged to take on new challenges learn continuously and contribute to impactful projects. This group is dynamic supportive and a great fit for professionals looking to build their career in semiconductors.
What Youll Do
Review design specifications and develop robust verification plans.
Build testbenches run simulations and debug failures to uncover design bugs.
Take initiative in leading planning and coordinating verification tasks with team members.
Create behavioral models of analog circuits.
Support bitmatching between RTL designs and MATLAB system models.
Integrate thirdparty VIPs for compliance testing of standard protocols.
Prepare design IP releases for customer delivery.
Collaborate in postsilicon validation and bringup efforts.
Work closely with crossfunctional teamsincluding Design Systems Analog Firmware and PDto ensure final verification closure.
Continuously improve verification methodologies tools and team processes.
What Youll Need
3 to 8 years of relevant experience in design verification.
Strong skills in SystemVerilog and UVM for constrainedrandom verification.
Experience verifying SerDes PHYs DSPs and mixedsignal analog designs.
Knowledge of Ethernet and PCIe protocols is highly desirable.
Familiarity with formal verification and poweraware UPF verification techniques.
Proficiency in SystemVerilog UVM Python Perl C/C and GNU Make.
Required Experience:
Senior IC
Full Time