What you do at AMD changes everything
At AMD we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in highperformance computing graphics and visualization technologies building blocks for gaming immersive platforms and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration respect and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo push boundaries deliver innovation and change the world. If you have this type of passion we invite you to take a look at the opportunities available to come join our team.
ASIC Physical Design Engineer
THE ROLE:
- The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency power and other design requirements for AMD next generation graphics processors in a fastpaced environment on cutting edge technology.
THE PERSON:
- Physical design Engineer with strong analytical thinking and problemsolving skills with excellent attention to detail. The candidates should have excellent communication skills very good team player and ability to drive lead and mentor team of engineers for project .
KEY RESPONSIBILITIES:
- Physical design of complex GPU multimillions gate design and achieve required performance area and power targets
- Work with RTL design to analyze potential bottlenecks for frequency resolve LOL and timing issue upfront in the project cycle to achieve frequency targets
- Handling Floorplan Physical Implementation of Powerplan Synthesis Placement CTS Timing Closure Routing Extraction Physical Verification (DRC & LVS) Crosstalk Analysis EM/IR
- Handling different PNR tools Synopsys ICC2 ICC Fusion Compiler PrimeTime StarRC Mentor Graphics Calibre Apache Redhawk Cadence Innovus genus
PREFERRED EXPERIENCE:
- 10 years of professional experience in physical design preferably with high performance designs.
- Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
- Experience in automated design flows for clock tree synthesis clock and power gating techniques scan stitching design optimization for improved timing/power/area and design cycle time reduction.
- Experience in floorplanning establishing design methodology IP integration checks for logic equivalence physical/timing/electrical quality and final signoff for large IP delivery
- Strong experience with tools for logic synthesis place and route timing analysis and design checks for physical and electrical quality familiarity with tools for schematics layout and circuit/logic simulation
- Experience in leading team of Engineers for design closure
- Versatility with scripts to automate design flow.
- Strong communication skills ability to multitask across projects and work with geographically spread out teams
- Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
- Excellent physical design and timing background.
- Experience in RTL design and LOL reduction is preferred
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.
- Proficient in perl python tcl etc
ACADEMIC CREDENTIALS:
- Bachelors or Masters in Electronics/Electrical Engineering
LOCATION:
Orlando FL Santa Clara CA Folsom CA Austin TX Boston
#LIPH1
Requisition Number:176681
Country:United StatesState:CaliforniaCity:Santa Clara
Job Function:Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age ancestry color marital status medical condition mental or physical disability national origin race religion political and/or third party affiliation sex pregnancy sexual orientation gender identity military or veteran status. Please click here for more information.