As a key player on the Design team you will participate in the development of the SoC CPU complex component (CPU NOC memory and peripherals) for Aevas 4D Lidar processing chip. You will be responsible for implementing and/or integrating subcomponents of the SOC.
What youll be doing:
Develop subcomponents of the SOC CPU complex.
Work with thirdparty IP providers including ARM.
Design and implement Aeva specific subcomponents.
Implement additional SOC functionality including functional safety and robustness functions.
Focus on developing efficient highly reliable highly available robust functionality.
Work with Architects design engineers and verification engineers and System software teams to ensure that the SOC meets its functional performance and power targets.
What youll have:
12 years of experience in design and verification of advanced ARMbased SOCs
Experience with ARMbased SOC design. Ability to achieve high performance and low power targets.
Experience writing Verilog RTL Code.
Working experience and knowledge in AMBA protocols CoreSight Debugger LPDDR Ethernet MIPI and highspeed serdes.
Proficient in debugging complex SOC or CPU core designs
Excellent verbal and written communication skills
Ability to collaborate deeply with crossfunctional leads and management teams
Ability to deliver results in a very fastmoving environment
Desire to learn & implement groundbreaking new processes and methodology for continuous improvement
Nice to haves:
Experience in presilicon validation on emulation platforms such as Cadence Palladium Mentor Veloce Synopsys Zebu
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