Staff Design Verification Engineer
Staff Design Verification Engineer
Posted on :
06-04-2025
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1 Vacancy
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Job Description
Role Summary
As a senior member of the DSP Design Verification team you will be playing a significant role in verifying the DSP design for new breeds of SoC and FPGA for advanced perception applications utilizing 4D Lidar. You will closely work with verification architects to define and develop verification environments for block subsystem and fullchip using constrained random verification techniques and verify complex DSP designs.
What youll be doing:
- Responsible for verifying stateofart DSP design at block subsystems and fullchip level verification environments.
- Define and develop testbenches constrained random verification environments reference models and scoreboards using SystemVerilog and UVM methodologies
- Built selfchecking environment using C/C reference models and DPI flow
- Verify DSP blocks against bitaccurate C/C reference models
- Define and execute verification plan for IP block subsystem and fullchip using SV/UVM methodology
- Work in a dynamic and fastpaced startup environment and work closely with a team of passionate engineers to enhance the existing processes methodology and tools to verify complex DSP and SoCs.
- Identify and write functional coverage groups to improve test/stimulus quality
- Through coverage analysis to identify verification gaps and achieve 100 coverage closure
- Work with the functional leads and crossfunctional teams to ensure highquality DSP IP delivery on time
What youll have:
- 12 years of experience in the design verification & validation of complex IPs SOCs
- Experience in verifying DSP design in advance
- 5 years in architecting and building constrained random verification environments reference models scoreboards and directed selfchecking tests using SV/UVM methodologies
- Solid programming skills in SystemVerilog UVM C/C Perl/Python.
- Proficient in debugging complex IP and SOC designs
- Excellent verbal and written communication skills
- Ability to collaborate deeply with crossfunctional leads and management teams
- Ability to deliver results in a very fastmoving environment
- Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement
Nice to have:
- Experience in developing C/C reference models and with Verilog DPI flow
- Experience in presilicon validation on emulation platforms such as Cadence Palladium Mentor Veloce Synopsys Zebu
- Postsilicon bringup and validation planning and
- Experience with test plan building tools like Vmanager.
- Experience with DFT verification.
Required Experience:
Staff IC
Employment Type
Full-Time
Key Skills
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