Physical Design Engineer
Physical Design Engineer
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Job Description
He / She should be able to do toplevel floor planning PG Planning partitioning placement scanchainreordering clock tree synthesis timing optimization SI aware routing timing analysis/closure and ECO tasks (timing and functional ECOs) SI closure design rule checks (DRC) and Logical vs. Schematic (LVS) checks Antenna checks. He / She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands Power Gating and substratebias.
Provide technical guidance mentoring to physical design engrs.
Interface with frontend ASIC teams to resolve issues.
Low Power Design Voltage Islands Power Gating Substratebias techniques.
Timing closure on DDR2/DDR3/PCIE interfaces.
Excellent communication skills.
Strong Background of ASIC Physical Design: Floor planning P&R extraction IR Drop Analysis Timing and Signal Integrity closure.
Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
Expertise in scripting languages such as PERL TCL.
Strong Physical Verification skill set.
Static Timing Analysis in Primetime or PrimetimeSI.
Good written and oral communication skills. Ability to clearly document plans.
Ability to interface with different teams and prioritize work based on project needs.
Employment Type
Full-Time
