For over 20 years IC Enable has successfully provided design IP IC products services and platform solutions to demanding customers ranging from startups to Fortune 50 members. Our design and product offerings focus on high reliability mixedsignal and digital markets while our platform solutions focus on IDM foundry and IP providers. Now is an exciting time to join our team as we continue to change the industry through experience in technology development fullcustom ASIC / SOC and electronics development across the Semiconductor Medical and Defense industries including some of the most challenging fabrication processes and product applications.
We are looking for an experienced Senior Circuit Design Engineer who has > 7 years of experience with custom Mixed Signal Circuit Design specifically in PLLs and associated subblocks including VCO chargepump dividers state machines LDO feedback and compensation techniques bandgap TDC interpolator circuits high speed buffers etc.
The right candidate must have Solid knowledge of Cadence/Synopsys EDA tools and practices for analog circuit design and a quality oriented mindset. We are looking for an individual with strong and effective communication skills that will positively impact our team culture.
Open Position: Key Responsibilities: - Design of analog building blocks for ROIC including multiGHz PLL sense amplifiers charge pumps bandgap serial interfaces
- Run pretapeout verification flows to confirm design meets performance power reliability and timing requirements
- Work closely with mask design engineers to deliver the physical design as well as define production/benchlevel test plans with postsilicon characterization groups for silicon evaluation to ensure interlocked and highquality .
- Work with team to ensure quality of final design delivery
- Create and maintain documentation for the related project work and may improve the design flow
- Lead/mentor junior engineers
Qualifications:
- MSEE/PhD with a minimum of 310 years experience or BSEE with 510 years experience. (MS or PhD preferred)
- Strong experience in the semiconductor industry required
- Handson design experience in performance analog and hybrid Phase Locked Loops analogtodigital (ADC) digitaltoanalog (DAC) data converter VCO LDO bandgap charge pump opamps interpolator circuits.
- Proficient with Cadence custom circuit design tools like ADEL and ADEXL and running MonteCarlo noise aging EM and IR drop simulations and stability analysis.
- Strong experience with simulation tools such as Spectre Hspice AFS and MATLAB System Verilog Python
- Capable of understanding DRC and LVS results with verification tools (Calibre ICV or like)
- Experience with the following is preferred; Digital PLL techniques TDC or DSP and control theory experience related to digital PLLs Dual chargepump PLL designs FractionalN PLLs spreadspectrum PLLs
- Experience with ROIC chips preferred
- Proficiency in scripting languages like Perl Python matlab etc. is preferred
- Able to work effectively in a team with good interpersonal skills enthusiasm and positive energy
- Possess strong analytical/problem solving skills and pronounced attention to details
- Must be a selfstarter and able to independently drive tasks to completion
At IC Enable we know that our most valuable asset is our team. We are seeking a candidate who is ready to dive into our culture and grow with our team. We build our team around those that are humble hungry and smart!
IC Enable benefits include Medical Dental Vision and Ancillary benefits 401K Plan with Company Match program
IC Enable is an Equal Opportunity Employer
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