Analog Layout Engineer
Analog Layout Engineer
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Job Description
Role: Analog Layout Engineer
Location: Santa Clara CA
Interview: Phone/Skype
Job Type: Contract
Job Description:
Senior layout designer responsible for layout of highperformance analog cores such as analogtodigital converters digitaltoanalog converters PLL transceivers etc. Leading IC layout of cuttingedge highperformance highspeed #CMOS integrated circuits in foundry CMOS process nodes in 3nm 5nm 7nm 16nm.
Qualifications:
Thorough knowledge of industry standard EDA tools from Cadence Mentor and Synopsys.
Ability to set up LVS #DRC ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with highperformance analog blocks (ADCs DACs PLLs etc.
Experience in floor planning block level routing and toplevel chip assembly.
Knowledge of highperformance analog layout techniques.
10 years of experience in highperformance analog layout in advanced CMOS processes.
Experience with #FinFET process nodes preferred.
Strong written and verbal communication skills.
Eligibility Criteria:
Genuine H1B candidates with verifiable I94 travel history (C2C acceptable).
Green Card & US Citizens will be considered only on W2 payment terms.
If you or someone you know is a strong match lets connect immediately!
Skills: #AnalogLayout #EDAtools #Cadence #Mentor #Synopsys #LVS #DRC #ERC #CMOS #HighPerformanceLayout
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Contract
Employment Type
Contract
