ASIC STA and CAD Methodology Expertise for High-Pe
ASIC STA and CAD Methodology Expertise for High-Pe
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Job Description
Total Experience 10 years
KEY RESPONSIBILITIES:
Developing block and SoC timing constraints full chip STA setup and signoff of multicorner multivoltage designs.
Owning timing flow and execution to meet SoC timing requirements including timing budgeting repeater planning constraints/exceptions generation and management
Engaging closely with block and SoC design teams to understand the design requirements STA constraints and convergence challenges.
Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures
PREFERRED EXPERIENCE:
10 years of professional experience in ASIC implementation and CAD methodology preferably experience closing timing of highperformance designs.
Demonstrated ability in areas of ASIC STA constraints generation timing analysis timing convergence and ECOs at both block and full chip level is a must
Implementation experience and knowledge handling multivoltage design is expected.
STA closure of low power and multipower mode designs is an added advantage.
Expertise in industry standard ASIC EDA tools including Synopsys DC and Primetime is required.
Proficiency in scripting language such as TCL Perl and/or Python
Experience developing scripts to automate design flow analysis
Handson experience with Physical Design implementation is a plus
Strong communication skills ability to multitask across projects and work with geographically spreadout teams
Strong analytical/problem solving skills and pronounced attention to details.
Regards
Mohammed Ilyas
PHor Textor You can share the updated resume at com
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Fulltime
Employment Type
Full-time
