System Verilog Jobs in Catania

Role Summary: Develop SV Real number and Verilog-AMS models for analog blocksFind design bugs/issues in Architecture/design of Analog/Mixed Signal IPs in terms of functional verification robustness checks with latest verification methodologiesTop level Analysis & verification of t More...

We are seeking creative and hardworking engineers to join our outstanding Analog/Mixed-Signal Verification team.You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan setup & execute AMS/UVM v More...

Role Summary: The Digital Design Engineer / Architect will be an integral member of highly experienced team in R&D. The individual is responsible for defining and realizing Digital functions on IPs Subsystem or IC level based on required specifications of high performance AC/DC an More...