Senior Analog IC Layout Engineer MCU

Role Summary

The Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog mixed-signal and custom IC designs. Working with a high degree of independence this role drives layout execution from floorplanning through tape-out ensuring that performance quality reliability and schedule objectives are achieved.

The position requires strong expertise in advanced layout methodologies excellent problem-solving capabilities and effective collaboration with design verification and technology addition to delivering critical project milestones the engineer provides technical guidance to less experienced engineers contributes to methodology improvements and plays a key role in mitigating project risks and supporting successful silicon delivery.

Key Responsibilities

• Lead the layout implementation of complex analog mixed-signal and custom digital blocks.
• Drive floorplanning device matching routing strategies and layout optimization to meet performance area power reliability and manufacturability requirements.
• Perform and review physical verification activities including DRC LVS ERC EM/IR latch-up density and reliability checks.
• Collaborate closely with design verification technology and product engineering teams to resolve layout-related challenges and achieve project milestones.
• Support advanced-node technologies including FinFET processes and contribute to methodology improvements and best practices.
• Provide technical guidance and mentorship to junior engineers and contractors.
• Assess project risks estimate layout effort and drive execution to meet aggressive schedules.

Expected Competencies

• Strong expertise in analog layout techniques matching shielding noise isolation ESD-aware layout power distribution and high-performance routing.
• Excellent understanding of semiconductor process technologies including planar and FinFET nodes.
• Proficiency with industry-standard EDA tools and physical verification flows.
• Ability to independently make technical trade-offs and solve complex implementation issues.
• Strong communication and stakeholder management skills.
• Proven track record of successful tape-outs and delivery of high-quality silicon.

Impact and Leadership

• Recognized technical expert within the layout organization.
• Influences project execution and physical design methodologies across multiple programs.
• Contributes to organizational capability growth through mentoring reviews and knowledge sharing.
• Plays a key role in achieving project schedules and silicon quality targets.

Qualifications

• BSEE or MSEE.
• Approximately 8-12 years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.
• Expert in Cadence Virtuoso XL Floorplanning Constraint Driven Layout and PVS DRC/LVS/ERC.
• Strong knowledge of matching common centroid shielding EM/IR high-speed routing parasitics and DFM practices.
• Proven experience leading analog-on-top and digital-on-top chip layouts.
• Experience with floorplanning power distribution ESD and multiple voltage domains.
• Familiarity with PLL OSC ADC DAC LDO Bandgap and high-speed interface circuits.
• Excellent communication and cross-functional leadership skills.
• Fluent in English
• SKILL or Perl scripting is a plus.

NXP is committed to equal pay for equal work and work of equal value and applies fair consistent and transparent remuneration practices.

As of the date of this posting the estimated gross annual base salary range for this position in Italy is between 50600 and 69600 annually. This range is intended as a guideline. Actual compensation may vary based on qualifications experience skills and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant the total compensation package may also include additional elements such as annual incentive opportunities and/or equity along with a competitive benefits package.

More information about NXP in Italy...

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