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Principal Analog IC Layout Engineer
Job Location:
Yearly Salary:
Posted:
9 October 2026 (Yesterday)
Posted:
Application Deadline:
6 January 2027
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
About the Team
NXP Semiconductors is seeking a Principal Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line with a primary focus on Automotive Power Solutions (APS).
The Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide. The team collaborates with Design Verification Package Test and Product Engineering organizations across a global R&D network to develop next-generation automotive and industrial semiconductor solutions.
Role Summary
The successful candidate will serve as a senior technical contributor within the Layout organization leading the physical implementation of complex automotive integrated circuits while driving methodology improvements technical excellence and project execution across multiple development programs.
Key Responsibilities
Technical Leadership
- Lead layout execution for complex mixed-signal and power management products.
- Define and drive floorplanning strategies from concept through tape-out.
- Act as a technical reference for layout methodologies flows and best practices.
- Support critical technical decisions impacting project execution and product quality.
Project Execution
- Drive challenging top-level layout developments.
- Anticipate technical risks and propose mitigation plans.
- Ensure compliance with design methodologies quality standards and tape-out requirements.
- Support project planning reviews and milestone execution.
Methodology and Continuous Improvement
- Contribute to layout productivity improvements.
- Drive methodology automation and tool enhancements.
- Promote reuse and standardization across projects and technologies.
- Share knowledge and lessons learned across worldwide teams.
Cross-Functional Collaboration
- Collaborate with Design Verification Package Test Product Engineering Reliability and Technology teams.
- Support issue resolution across multiple engineering disciplines.
- Mentor and technically guide layout engineers across the organization.
Required Skills
- Master Degree in Electrical Engineering Electronics Physics or Microelectronics.
- Extensive experience in Analog IC Layout development.
- Expert knowledge of Cadence Virtuoso Calibre and physical verification flows.
- Strong expertise in mixed-signal BCD and High Voltage technologies.
- Proven experience leading complex top-level layout activities.
- Strong understanding of layout quality reliability and manufacturability.
- Excellent communication and stakeholder management skills.
- Fluent English.
Preferred Qualifications
- Experience with automotive semiconductor products.
- Experience with layout automation and scripting (SKILL Python TCL).
- Multi-technology expertise.
- Experience driving methodology improvements across organizations.
- Experience in international R&D organizations.
NXP is committed to equal pay for equal work and work of equal value and applies fair consistent and transparent remuneration practices.
As of the date of this posting the estimated gross annual base salary range for this position in Italy is between 61000 and 83900 annually. This range is intended as a guideline. Actual compensation may vary based on qualifications experience skills and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant the total compensation package may also include additional elements such as annual incentive opportunities and/or equity along with a competitive benefits package.#LI-6710Required Experience:
Staff IC
About Company
NXP is a global semiconductor company creating solutions that enable secure connections for a smarter world.
