Principal Verification Engineer

Job Description ASIC/SoC Verification Engineer

We are seeking an experienced Principal ASIC/SoC Verification Engineer to join our dynamic and fastpaced engineering this role you will be responsible for ensuring the functional correctness robustness and overall quality of our cuttingedge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges this opportunity is an excellent fit.

#LI-VS1

1. Verification Planning and Execution

• Develop and execute comprehensive SoC/IPlevel verification plans aligned with design specifications and project goals.
• Drive verification closure through functional code and assertion coverage ensuring highquality deliverables.
• Apply industrystandard ASIC/SoC verification techniques including test planning testbench creation constrainedrandom and directed stimulus assertions and coveragedriven verification.
• Perform SoC integration verification validating interactions across subsystems interfaces and power/performance domains.

2. Testbench & Environment Development

• Architect develop and enhance SystemVerilog UVM/OVMbased testbenches for IP and SoClevel verification.
• Build and integrate reusable Verification IP (VIP) and scalable verification components.
• Collaborate with internal teams and thirdparty VIP providers to ensure seamless integration and compliance.
• Develop checkers scoreboards monitors and coverage models to support robust verification.

3. Methodology Flows & Best Practices

• Demonstrate strong understanding of ASIC/SoC design and verification methodologies including constraintrandom verification and objectoriented programming principles.
• Contribute to verification methodology improvements automation and flow optimization.
• Ensure adherence to best practices in UVM architecture reuse and maintainability.

4. Advanced Verification Skills

• Perform GateLevel Simulation (GLS) including SDF annotation timing verification and debug of postsynthesis/postlayout issues.
• Execute poweraware verification using UPF/CPF validating power modes isolation retention and sequencing.
• Debug complex SoClevel issues involving multiple clock domains resets and power states.
• Apply formal verification techniques where appropriate to complement simulationbased verification.

5. Technical Skills

• Strong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python Perl Tcl C/C++ and Verilog PLI.
• Familiarity with standard protocols and interfaces (e.g. I2C SPI UART AXI/AHB/APB).
• Experience with simulation debug and coverage tools from major EDA vendors (Synopsys Cadence Siemens).
• Knowledge of CI/regression automation version control and workflow tools is a plus.

6. Collaboration & Communication

• Work effectively with design architecture DV validation and firmware teams to drive verification to completion.
• Communicate technical concepts clearly through documentation reviews and crossfunctional discussions.
• Demonstrate initiative strong analytical problemsolving skills and adaptability in a diverse team environment.

#LI-VS1

Required Qualifications

• Bachelors or Masters degree in Electrical Engineering Computer Engineering or related field.
• 10 Years of experience in SoC/IP verification.
• Strong expertise in SystemVerilog UVM and advanced verification methodologies.
• Hands-on experience with ARM-based SoC architectures AMBA protocols (AXI/AHB/APB) and system-level interactions.
• Proven ability to build reusable scalable testbench architectures.
• Solid understanding of test planning coverage-driven verification and verification metrics.
• Experience with GLS timing verification and debug.
• Knowledge of power-aware verification (UPF/CPF).
• Strong scripting and automation skills (Python Perl Shell Make etc.).
• Exposure to AI/ML techniques applied to verification (e.g. intelligent stimulus generation failure triage coverage optimization).
• Excellent problem-solving debugging and communication skills.

#LI-VS1