Physical Design Engineer with RTL Design Background

About TI

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the worlds brightest minds TI creates innovations that shape the future of technology. TI is helping about 100000 customers transform the future today. Were committed to building a better future from the responsible manufacturing of our semiconductors to caring for our employees to giving back inside our communities and developing great minds. Put your talent to work with us change the world love your job!

About the Role:

Are you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a Physical design engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance.

We are seeking a skilled Digital Physical Design Engineer of 2-5 Year of industry experience with good RTL design hands-on and understanding. The candidate will be responsible for taking RTL through synthesis floorplanning place-and-route timing closure power optimization and physical verification to tape-out. This role demands hands-on expertise in EDA tools physical design flows and deep knowledge of digital VLSI concepts.

Key Responsibilities:

• Execute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.
• Perform logic synthesis floor-planning placement clock tree synthesis (CTS) and routing.
• Develop/support/update design constraints.
• Drive timing closure across multiple corners and modes using static timing analysis (STA).
• Good understanding of digital timing analysis
• Optimize for area power and performance (PPA) at block and chip level.
• Conduct physical verification: DRC LVS Antenna checks IR-drop and EM analysis.
• Develop/support/update constraints.
• Collaborate with RTL design verification and architecture teams to resolve design and implementation issues.
• Provide EDA flow automation support (scripting in TCL/Perl/Python).
• Contribute to design reviews documentation and sign-off processes for successful tape-out.
• Highly prefer if additionally able to handle RTL coding Digital QC(RDC/CDC/Lint). Contribute to digital design reviews and Arch reviews.

Required Skills & Qualifications:

• B.E./ or M.E./ in Electronics Electrical VLSI or related field.
• 2-5 years of hands-on experience in physical design for ASIC/SoC.
• Strong knowledge of CMOS VLSI design fundamentals and digital circuit concepts.
• Proficiency in EDA tools such Cadence (Innovus Tempusvoltus ) or equivalent.
• Experience in signoff checks: DRC LVS IR drop EM noise analysis.
• Strong scripting skills (Tcl Perl or Python) for flow automation.
• Excellent problem-solving debugging and analytical skills.
• Expertise in timing analysis floorplanning placement CTS routing and optimization techniques.
• Hands-on of cadence simulation tools.
• Knowledge of audio signal chain I2C ASI/TDM memory architecture and FPGA is preferred.
• Excellent debugging and problem-solving skill.

Additional preference:

• Digital design fundamentals and basic electrical/electronic engineering concepts.
• Hands-on experience in RTL design coding along with understating of QC (Lint/CDC/RDC) is highly preferred and recommended.

Soft Skills:

• Strong communication presentation and collaboration skills.
• Ability to work in a fast-paced deadline-driven environment.
• Self-motivated and detail-oriented with a commitment to quality.