HighSpeed RTL Design Engineer

Key Responsibilities

HighSpeedRTL Design & Implementation

• Design and implementtimingcriticalRTL blocks including:

• Control and sequencing FSMs

• Powerup shutdown andmodetransitionlogic

• Register banks and configuration logic

• Telemetry and monitoringdatapath

• Develop RTL with attention tolatency deterministic behaviorracefreelogic and metastability avoidance.

NanometerProcessAwareRTL Coding

• Write RTL that is robust to:

• Tight setup and hold margins

• Clock skew and uncertainty

• Multicycleandfalsepathconstraints

• Process voltage and temperature (PVT) variation

• Ensure RTL isclean for synthesis static timing analysis and ECO cyclesin sophisticated technology nodes.

Clocking Reset &PowerAwareLogic

• Implement and reviewclockdomaincrossings (CDC)using proven synchronization techniques.

• Designreset and initialization logicto ensure predictable system startup and recovery.

• Supportpowerawareandmodedependentbehavioras the need arises by system operation.

Integration & Debug

• Integrate RTL blocks into larger subsystems ortopleveldesigns resolving:

• Portlistmismatches

• Clock and reset dependencies

• Mode interaction issues

• Debug RTL and integration issues using simulation waveforms and tool feedback.

Verification & Timing Closure Support

• Work closely with verification engineers to:

• Clarify design intent and corner cases

• Fix RTL issues uncovered during verification

• Address timing issuesidentifiedduring synthesis orplaceandroutebyrefining logic simplifying control paths or adding limited pipelining under guidance.

Design Reviews & Documentation

• Participate actively inRTL and design reviews incorporating feedback from senior engineers.

• Maintainclear documentationdescribing block functionality assumptions and known limitations.

Required Technical Skills

RTL & Digital Design

• StrongproficiencyinSystemVerilog/ Verilog RTL
  

Experience with:

• FSM design and implementation

• Reset synchronization

• Clockdomaincrossing concepts

• Solid understanding oftimingcriticalcontrol logic.

HighSpeed& System Awareness

Solid understanding of:

• Setup/hold timing fundamentals

• Criticalpathsensitivity

• Multimode and settingsbased behavior

• Exposure tomixedsignalinteraction(digital logic controlling or responding to analog behavior).

Flow Awareness

• Familiarity with:

• RTL lint and CDC checks

• Synthesis and basic STA reports

• DFTfriendlyRTL practices

• UPF and LEC

• Ability to debug issues exposed duringRTLsignoffor late integration stages.

GoodtoHave or equivalent experience

• Experience withPMICsmixedsignalSoCs or companion ICs

• Exposure to industry-standard specifications

• Basic scripting skills (Python /Tcl) for automation

• Experience working acrossRTLDVPD handshakes

Behavioral Expectations

• Works independently on assigned RTL modules or subsystems

• Raises risks early with analysis and proposed solutions

• Demonstrates growing ownership of RTL quality and delivery

• Learns from reviews and feedback to deepenhighspeeddesignexpertise

• Effective and compliant use of Micronapproved AI tools to augment verification activities improve execution efficiency and support continuous improvement.