DFT Digital Design Engineer (fmd)

Scope of Responsibilities/Expectations

• Support the implementation and integration of Design for Test (DfT) for complex SoC and semiconductor products.
• Participate in DfT implementation activities including Scan MBIST Boundary Scan (JTAG) Logic BIST test compression ATPG pattern generation fault simulation and DfT verification.
• Assist in the development verification validation and integration of test structures throughout the SoC design cycle to achieve manufacturing test coverage silicon quality and product reliability goals.
• Perform DfT-related checks analyze fault coverage and test results and support debug of DfT issues during design verification silicon bring-up characterization and yield improvement activities.
• Work closely with Design Verification Physical Design Product Engineering and Test Engineering teams to support DfT integration validation and product development.
• Assist in developing scripts and automation solutions to improve DfT productivity flow efficiency and methodology execution.
• Create maintain and improve DfT documentation implementation guidelines methodologies design standards and lessons learned.
• Demonstrate continuous learning and contribute to the advancement of DfT methodologies semiconductor test technologies and best practices.
• Perform assigned DfT tasks under the guidance and mentorship of senior engineers.

Specific Knowledge/Skills

• Bachelors or Masters degree in Electrical Engineering Electronic Engineering Computer Engineering Computer Science or a related field.
• Good understanding of digital design fundamentals including combinational and sequential logic finite state machines computer architecture fundamentals and RTL design using Verilog/SystemVerilog.
• Basic understanding of CMOS design principles semiconductor manufacturing concepts ASIC/SoC design flows and manufacturing test methodologies.
• Exposure to or basic understanding of DfT concepts including scan architecture ATPG fault models MBIST Boundary Scan (IEEE 1149.1/JTAG) Logic BIST fundamentals and test compression techniques.
• Familiarity with simulation methodologies debugging techniques waveform analysis and DfT verification flows.
• Understanding of timing synthesis and physical design concepts.
• Familiarity with Linux/Unix environments and exposure to scripting languages such as Python Tcl Perl or Shell.
• Familiarity with EDA tools used for digital design verification implementation and DfT flows.
• Strong analytical logical reasoning debugging and problem-solving skills with the ability to break complex problems into manageable components.
• Self-motivated detail-oriented and committed to quality execution excellence and continuous improvement.
• Excellent written and verbal communication skills.
• Ability to work effectively in cross-functional teams manage multiple priorities learn through technical mentorship and collaborate in a dynamic development environment.
• Strong curiosity willingness to learn and passion for semiconductor and test technologies.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications therefore a conscious and reliable way of working is necessary.

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