Senior Engineer-ASIC Design

Our vision is to transform how the world uses information to enrich life for all.

We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.

Your responsibilities will include but are not limited to the following:

This role is for a core technical individual contributor responsible for development of IPs and subsytem integration for controllers. You will be responsible to analyses design requirements architecture specification and come up with microarchitecture and design specification. You will be responsible for design development bring up design using own methods of verification (Formal or Unit testbench). In daytoday work need to interact with DV for smooth IP development. You need to work on FW flow initialization sequence for IP bring up. This Role requires knowledge and experience in working with systems based on PCIe/NVMe/AXI/DDR etc. The position will require hands on experience in RTL logic coding simulation and debugging. This is a highly visible and challenging role with lot of learning and future growth.

Strong fundamental knowledge of digital design Verilog and scripting language

Experience with microarchitecture and synchronous and Asynchronous digital designs

Working experience of Synthesis STA Lint & CDC

Excellent problemsolving skills.

Team player with great interpersonal communication skills.

Ability to work with local and remote teams Design/Verification

This role is based out of Bangalore location.