NXP Semiconductors Romania

As Senior Data Engineer you will assist in designing developing and maintaining integration solutions that connect various business application and systems. With other words you will ensure maximum effectiveness and quality of implementing IT integration solutions for NXP. You are man

As Senior Data Engineer you will assist in designing developing and maintaining integration solutions that connect various business application and systems. With other words you will ensure maximum effectiveness and quality of implementing IT integration solutions for NXP. You are man

Responsibilities: To define the FPGA development plan according to the requirement from design or software teamPorting internal ASIC design to FPGA platformTo setup FPGA simulation environment Co work with validation team to define pre-silicon validation test plan and do resource esti

Responsibilities: To define the FPGA development plan according to the requirement from design or software teamPorting internal ASIC design to FPGA platformTo setup FPGA simulation environment Co work with validation team to define pre-silicon validation test plan and do resource esti

Responsibilities:The Analog Circuit Development Engineer / Architect is responsible for defining and realizing Analog functions on IPs Subsystem or IC level.The individual is responsible for design verification and evaluation of those.The individual is accountable for designing accord

Responsibilities:The Analog Circuit Development Engineer / Architect is responsible for defining and realizing Analog functions on IPs Subsystem or IC level.The individual is responsible for design verification and evaluation of those.The individual is accountable for designing accord

Responsibilities:Setup and maintain DFT flow familiar with script language.Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion ATPG generation test patterns generation.Experience RTL/netlist simulation good debug capab

Responsibilities:Setup and maintain DFT flow familiar with script language.Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion ATPG generation test patterns generation.Experience RTL/netlist simulation good debug capab

Responsibilities:Sample reception / collection / distribution / weekly shipment system implementationWeekly GC FQE individual EEN influx data monitor and releaseMonthly GC overall non GC initiation and GC FQE individual EEN reduction data collection Export control register for all CQC

Responsibilities:Sample reception / collection / distribution / weekly shipment system implementationWeekly GC FQE individual EEN influx data monitor and releaseMonthly GC overall non GC initiation and GC FQE individual EEN reduction data collection Export control register for all CQC

Provide support for Reliability analysis including but not limited to:1. Environmental Stressing (Temp cycle UHAST HTSL MSL)2. Physical Analysis (CSAM Solderability)3. Support RAP execution.4. Incoming & Outgoing sample trackingJob Qualification Complete SPM result 5 credit result or

Provide support for Reliability analysis including but not limited to:1. Environmental Stressing (Temp cycle UHAST HTSL MSL)2. Physical Analysis (CSAM Solderability)3. Support RAP execution.4. Incoming & Outgoing sample trackingJob Qualification Complete SPM result 5 credit result or

Prepare IFRS and/or local GAAP financial statements and notes management reports and other related documents required for local statutory reporting for a group of countries under your responsibility in Finance Center of Excellence (FCOE).Identify calculate and post all necessary GAAP

Prepare IFRS and/or local GAAP financial statements and notes management reports and other related documents required for local statutory reporting for a group of countries under your responsibility in Finance Center of Excellence (FCOE).Identify calculate and post all necessary GAAP

Location- Hsinchu / TaipeiBusiness Line Connectivity & SecurityJob DescriptionsSoftware engineer will participate in Wi-Fi software/firmware design and development.Research design and develop cutting edge technologies for industrial features and IEEE/WFA spec. Ranging from Wi-Fi ente

Location- Hsinchu / TaipeiBusiness Line Connectivity & SecurityJob DescriptionsSoftware engineer will participate in Wi-Fi software/firmware design and development.Research design and develop cutting edge technologies for industrial features and IEEE/WFA spec. Ranging from Wi-Fi ente

Role Summary: leading and managing all the activities of Assy EOL(End of Line) Operations in ATBK ensuring delivery on time with zero defect to customer with competitive costs to meet business objectives.Job Responsibility: Management Team member of NXP Bangkok to drive site decision

Role Summary: leading and managing all the activities of Assy EOL(End of Line) Operations in ATBK ensuring delivery on time with zero defect to customer with competitive costs to meet business objectives.Job Responsibility: Management Team member of NXP Bangkok to drive site decision

The Product Diagnostic & Quality Center (PDQC) is seeking an experienced Hardware Validation Engineer to support the validation of electrical test hardware for NXP product analysis. The ideal candidate will have a strong Test Engineering background and experience. This role involves v

The Product Diagnostic & Quality Center (PDQC) is seeking an experienced Hardware Validation Engineer to support the validation of electrical test hardware for NXP product analysis. The ideal candidate will have a strong Test Engineering background and experience. This role involves v

Responsibilities:Participate in DFT feature and architecture definition for complex SOCImplement DFT logic/circuit including SCAN Boundary SCAN MBIST Analog Macro test logicGenerate DFT related timing constraints and support timing closure with backend engineerDFT test patterns genera

Responsibilities:Participate in DFT feature and architecture definition for complex SOCImplement DFT logic/circuit including SCAN Boundary SCAN MBIST Analog Macro test logicGenerate DFT related timing constraints and support timing closure with backend engineerDFT test patterns genera

Review reliability qualification strategies to meet the NXP Reliability Policy and Requirement (RPR) and Customer specific requirement.Peer of local and global reliability qualification process regarding to reliability knowledge to participate a thorough risk-analysis based on FMEA an

Review reliability qualification strategies to meet the NXP Reliability Policy and Requirement (RPR) and Customer specific requirement.Peer of local and global reliability qualification process regarding to reliability knowledge to participate a thorough risk-analysis based on FMEA an

ResponsibilitiesResponsible for analog / mixed-signal IP design for ARM-based MCU/MPU product developmentIP schematic design / analog & mix-signal simulation/ layout design / IP view generation / technical documentationWork with SoC / Backend team on IP integration.RequirementsMaster

ResponsibilitiesResponsible for analog / mixed-signal IP design for ARM-based MCU/MPU product developmentIP schematic design / analog & mix-signal simulation/ layout design / IP view generation / technical documentationWork with SoC / Backend team on IP integration.RequirementsMaster

Role Summary locally drive the lead products ramp up under new technology introduction (NTI) and within foundry process transfers and new fab enablementJob Description:Close collaboration with foundries NXP technology groups the business lines and various other stakeholders to qualify

Role Summary locally drive the lead products ramp up under new technology introduction (NTI) and within foundry process transfers and new fab enablementJob Description:Close collaboration with foundries NXP technology groups the business lines and various other stakeholders to qualify

Job DescriptionDrive to achieve test operation KPIs across quality cost and deliveryEngineering support on daily test operations and ensure continuous supply chain and delivery to customerDrive qualifying new test hardware/facility at subcontractor factoriesParticipate in new process/

Job DescriptionDrive to achieve test operation KPIs across quality cost and deliveryEngineering support on daily test operations and ensure continuous supply chain and delivery to customerDrive qualifying new test hardware/facility at subcontractor factoriesParticipate in new process/

The Semiconductor Process Integration Lead/Architect works and is responsible for ton technology selection development enablement and transfers of integrated silicon technology.Responsibilities:Process integration / device lead in technology development and transfer projects.Collabora

The Semiconductor Process Integration Lead/Architect works and is responsible for ton technology selection development enablement and transfers of integrated silicon technology.Responsibilities:Process integration / device lead in technology development and transfer projects.Collabora

Job Descriptions -The selected candidate will participate in Wi-Fi/BT software/firmware design implementation integration validation and maintenance phases for standard based and non-standard based Wi-Fi/BT/BLE products for IOT and automotive markets. - Lead/participate in complex fe

Job Descriptions -The selected candidate will participate in Wi-Fi/BT software/firmware design implementation integration validation and maintenance phases for standard based and non-standard based Wi-Fi/BT/BLE products for IOT and automotive markets. - Lead/participate in complex fe

Responsibilities:Develop and optimize Embedded MLinference engines for microcontrollers.Train and fine-tune machine learning models using TensorFlow and PyTorch to be deployed on resource-constrained devices.Implement and experiment with techniques to improve model performance on low-

Responsibilities:Develop and optimize Embedded MLinference engines for microcontrollers.Train and fine-tune machine learning models using TensorFlow and PyTorch to be deployed on resource-constrained devices.Implement and experiment with techniques to improve model performance on low-

Responsibilities:Support wireless connectivity (Wi-Fi Bluetooth Zigbee etc.) solution integration and bring-upDebug and resolve issues (system software etc.) reported by customersDrive internal co-work and provide customer support timelySupport internal development and debug tasks as

Responsibilities:Support wireless connectivity (Wi-Fi Bluetooth Zigbee etc.) solution integration and bring-upDebug and resolve issues (system software etc.) reported by customersDrive internal co-work and provide customer support timelySupport internal development and debug tasks as

Responsibilities:Develop / port / maintain testing for MCU ROM software and tools to ensure functionality compatibility performance and stability.Validate ROM software for MPU/MCU chips on FPGA/Zebu environment and reference boards.Design / develop / use test tools for automatic test

Responsibilities:Develop / port / maintain testing for MCU ROM software and tools to ensure functionality compatibility performance and stability.Validate ROM software for MPU/MCU chips on FPGA/Zebu environment and reference boards.Design / develop / use test tools for automatic test