Employer Active
Role- Sr. Digital Low Power Implementation Engineer
Location Pleasanton CA or Austin, TX
Rate- $70/hr - 80/hr
Client- Alif Semiconductor
Responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints.
As a Sr. Digital Implementation Engineer, you will own the UPF delivery (to Design Verification and Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the libraries and models and tool inter-operability. This position requires expert knowledge of Low Power ASIC implementation flow (including STA/DFT and IP integration)
Define and document UPF-based low power methodology and scripts/flows
UPF hand-off checks (Conformal-LP, Xcelium, Genus/Innovus)
UPF requirements and generation for defining power intent (at ip, block and chip level)
Interface with Physical Design for design partitioning, floorplan and timing closure
Analyze UPF implementation results and facilitate design changes and ECOs with front-end and back-end teams
Minimum Qualifications:
Expert knowledge and significant experience with UPF-based low power ASIC Implementation Flow, UPF Generation/Validation and Timing Closure
Experience in low power design issues, tools, and methodology including UPF power intent specification
Familiarity with Synthesis (Cadence), DFT (Tessent) and back-end (Cadence) tools
Proficient in Verilog/SV/Tcl/Perl/Python
Highly motivated to debug and resolve CAD tool flow issues
Self-starter with good analytical, problem solving and communication skills
Bachelor's degree in Electrical Engineering, a related discipline, or equivalent experience
Desired Qualifications:
Experience with IP integration
Experience with Cadence UPF and ECO Flow
Experience with Clock Domain Crossing (CDC) Analysis
Experience with timing corners and library models
Proven track record of successful deep submicron technology node tapeout (including Silicon bring-up)
Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)
Full Time