RTL engineer

THE ROLE:
We are searching for a senior RTL engineer to join the PLL design team responsible for defining specifying modeling and implementing RTL for current and future advanced PLL IPs

Join a dynamic team and give a boost to your personal career in a challenging and fascinating evergrowing neverboring area! Looking forward to welcoming you in the team!

THE PERSON:
The successful candidate will possess:
Excellent analytical and critical thinking skills along with attention to details
Must be an initiativetaker able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic teamfirst mentality
Ability to provide mentorship and guidance to junior engineers
Relevant academic background (M. degree preferred) and at least 5 years progressive experience

KEY RESPONSIBILITIES:
Analyze complex digital design problems and propose solutions
Develop Verilog RTL and Functional Behavioral Models
Drive/develop ASIC design flows and scripts
Create microarchitecture specifications
Work with Design Verification team to ensure functional correctness
Work with Physical Design team to ensure proper implementation of the design along with timing closure
Deliver improvements optimization and power saving enhancements
Support silicon bringup and diagnostics

PREFERRED EXPERIENCE:
Proven experience in analog mixed signal design from specification to successful silicon
Experience in highspeed interfaces such as DDR GDDR HBM and/or high speed SERDES
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in industry standard ASIC CAD tools for simulation synthesis STA CDC UPF power estimation etc.
Experience in advanced semiconductor technologies preferably FinFET
At least 5 years progressive experience in RTL Design