RTL design engineer
Posted on :
28-03-2023
Employer Active
1 Vacancy
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Job Description
Req ID : 1999524
candidate Roles and Responsibilities
Collaboration with offshore team.
IC role and offshore task coordination
Must have 10+ yr experience with ASIC design activities Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations.
Preferred:
Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols.
Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must.
Skills :
Employment Type
Full Time
Company Industry
Key Skills
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