Pre-Silicon Validation PCIe Gen 5 and NVMe experience SV and UVM San Jose CA
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Job Description
Greetings
We have the below requirement with our Client. Kindly go through the JD below and let me know your interest
Role name: Engineer
San Jose CA
Duration : 10months
Role Description:
Perform presilicon validation for customers flagship silicon
Liaise with design teams Communicate and coordinate with offshore teams
Be the main interface for the customer
Competencies: EIS : ASIC Frontend Modelling RTL design and Implementation
Experience (Years): 810
Essential Skills: PCIe (Gen 5) and NVMe experience SV and UVM
Desirable Skills: PCIe (Gen 5) and NVMe experience SV and UVM
Keywords: PreSilicon Validation PCIe (Gen 5) and NVMe experience SV and UVM
Best Regards
Employment Type
Full Time
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