Engineer FPGA Design - III

PDA Engineer
100% Remote
Laptop will be issued Dont submitted same candidates between JP25804 & JP 25805 (same sponsor)

Description:
Advanced Design is always the first design team at Intel tackling the challenges of scaling technology to the cadence of Moores Law. We work with industry leading design and process technologists to enable breakthroughs in power performance and density as we enable our product design partners to bring worldclass products to the market. Join us for a fastpaced dynamic and richly rewarding experience on the forefront of technology.
This position within the Advance Design Group oversees definition design verification and documentation for SoC (System on a Chip) development. Determines architecture design logic design and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries functional units and subsystems into SoC full chip designs Register Transfer Level coding and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis place and route timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure conducts experimental tests and evaluates results. May also review vendor capability to support development.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a positive factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3 years of experience or MS degree with 2 years of experience or PhD degree with 1 years of experience in Electrical Computer Engineering or related field.
6 years of experience in the following:
IP/SoC physical design optimization and methodologies for optimal Performance Power Area and Cost (PPAC).
Experience driving physical design EDA tools design reference and signoff flows in advanced process technologies DTCO PPA and EDA vendor engagement.
Lowpower and multiple clock domain design.
Scripting skills using a programming language such as Python TCL.
Experience in driving SoC digital design execution on leading edge technologies.
Experience in using Fusion compiler ICC2 DC


Preferred Qualifications:
8 years of experience in the following:
All aspects of VLSI Design from standard cell architecture to physical design and signoff flows
Multiple chip tapeout experience on leading edge semiconductor nodes.
YoE and skillset to match the Preferred Qualifications
Prefer experience with Intel flows and tools