Design Verification Engineer

Job Title: Verification Engineer Location: San Jose, CA

POSITION SUMMARY

QUALIFICATIONS: Education Requirements BS/MS in EE/CE, plus 5+ years of Design Verification experience Familiarity with ASIC, Computer and Embedded Systems Architectures Excellent oral and written communication skills with people at all levels, a must. Team player, with excellent debugging skills

Skills/Experience Mandatory Experience o Writing and maintaining test plans o Creating and maintaining UVM testbenches o Created a module testbench from scratch o Written Cover points, Assertions (SVA) and closed coverage o Knowledge of standard bus protocols such as AHB, AXI, etc.

Desirable Experience o Scripting and test automation for regression o Experience with PCIe/NVMe and/or ONFI o Experience with SSD architecture