DeltaV hardware engineer

Job Description

Responsibilities

• Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture design and verification
• IPs integration
• Understand Design for Verification concepts
• Drive the toplevel Architecture definition and develop the necessary RTL
• Drive the chiplevel integration verification plan development and verification
• Supervise the RTLtoGDS flow and assist with synthesis and timing closure
• Support the test program development chip validation and chip life until production maturity
• Work with FPGA engineers to perform early prototyping
• Support handoff and integration of blocks into larger SOC environments
• Assist with Algorithm analysis verification and improvement
• Contribute to ASIC digital architecture design and verification

Skills

Must Have:

5 years of FPGA design experience using Verilog SystemVerilog

• 5 years of experience in AMD/Xilinx FPGA design (Kintex/Virtex UltraScale desired 7series minimum)
• 4 years of experience as a Digital Design Engineer and/or a Chip Lead
• Experience in RTL coding synthesis and/or SoC Integration
• Experience in digital design Architecture
• BS Electrical Engineering/Computer Science or equivalent experience
• Experience with UPF based simulation flow
• System Verilog OVM/UVM experience
• Tcl and Python (or similar) scripting experience
• Experience in SoC integration and ASIC architecture

Wish List/ Nice to Have:

• Experience in DFT/Testability requirement and test program definition
• Experience using High Speed interfaces like PCIe USB MIPI
• FPGA design
• Tensilica DSP TIE CNN fixed point floating point python.
• Experience with Power Aware GLS flow
• MSEE/CS or equivalent experience

Qualification:

Must have skills:

1 FPGA design experience using Verilog SystemVerilog AMD/Xilinx FPGA design (Kintex/Virtex UltraScale desired 7series minimum)

2 RTL coding synthesis and/or SoC Integration

3 Comms working with other engineers being proactive

Nicetohave Skills: 1 Experience using High Speed interfaces like PCIe USB MIPI

2 Experience in DFT/Testability requirement and test program definition