SoC Architect Low Power Design ( HBM)

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using theirexpertisein the relentless pursuit of innovation for customers and partners. The solutions we build enable everything from AI acceleration andhighperformancecomputing tonextgenerationmemory systems. We do it all while committing to integrity sustainability and giving back to our communitiesfueling the innovation we pursue.

As a Low Power Architect you will be a key technical leader within the Heterogeneous Integration Group (HIG) responsible for defining modeling and drivingSoClevelpower architecture fornextgenerationHBM logic die andmemorycentricSoCs. You will work across architecture RTL verification physical design firmware and product teams to deliverindustryleadingperformanceperwattsolutions under aggressive power thermal and reliability constraints.

This role combinessystemlevelarchitectural ownership with deep collaboration through implementation and siliconbringup.

Key Responsibilities

• Define and ownSoClevellowpowerarchitecture including power domains voltage islands clocking strategies andlowpoweroperating modes (active idle retention sleep).

• Develop power performance and thermal models to evaluate architectural tradeoffs and guide PPA optimization across workloads and use cases.

• Architect and drive implementation of power management features such as DVFS clock gating power gating retention strategies and adaptive performance controls.

• Collaborate with SoC and subsystem architects to translate product requirements intopowerawaremicroarchitecturalspecifications.

• Partner closely with RTL verification and physical design teams to ensure correct and efficient implementation of power intent (e.g. UPF/CPF) including debug ofpowerrelatedfunctional and timing issues.

• Work with firmware and software teams to definehardwaresoftwarepower management interfaces sequencing and control flows.

• Drive performance vs. power analysis to support product decisions roadmap planning and customer requirements.

• Supportpresiliconvalidation andpostsiliconbringup including silicon power characterization correlation to models androotcauseanalysis.

• Contribute to architectural documentation design reviews andcrossfunctionaltechnical discussions.

• Mentor junior architects and engineers promoting best practices inlowpowerdesign.

Qualifications

• Strong experience in SoC orsystemlevelarchitecture with a focus onlowpowerorenergyefficientdesign.

• Deep understanding of power management techniques: DVFS power gating clock gating voltage regulation andlowpowerstate machines.

• Experience with power modeling analysis andtradeoffstudies at system and block level.

• Familiarity with hardware/software interactionsimpactingpower efficiency.

• Working knowledge of RTL design concepts andlowpowerimplementation flows (SystemVerilog UPF/CPF).

• Experience across theRTLtoGDSflow including synthesis STA and powersignoffconsiderations.

• Strongcrossfunctionalcommunication and technical leadership skills.

• Programming or scripting experience (e.g. Python C/C TCL).

• Ability to work effectively in a global engineering environment.

Preferred Qualifications

• Experience with HBM DRAM ormemorycentricSoCs.

• Background in GPU CPU orhighperformanceaccelerator architectures with aggressive power targets.

• Familiarity with industry power standards and frameworks (e.g. ARM power management conceptsSCMIlikeinterfaces).

• Exposure to silicon power measurement lab characterization orpostsilicondebug.

• Experience with emulation or prototyping platforms.

• Masters or PhD in Electrical Engineering Computer Engineering or related field.

• 10 years of relevant industry experience withdemonstratedarchitectural ownership and mentorship.