STA Engineer Top Level (Senior)

Our client is expanding their Physical Design and timing function and is looking for a Senior STA Engineer Top Level to support timing constraints and timing closure across complex SoC designs.

In this role you will create review and verify block and top level timing constraints. You will work closely with physical implementation RTL verification and architecture teams to ensure clean and reliable timing closure for advanced semiconductor programs.

Location: Barcelona Spain - Hybrid

Responsibilities:

As a Senior STA Engineer Top Level your broad responsibilities will include but are not limited to:

Create and verify block and top level timing constraints
Support static timing analysis across complex SoC designs
Work with implementation teams to resolve timing issues
Define and review SDC constraints
Support clock strategy reset strategy and timing exceptions
Collaborate with RTL physical implementation and architecture teams
Analyze timing reports and drive closure actions
Contribute to timing methodology improvements
Support tape out readiness from a timing perspective

Requirements:

Our client offers an exciting challenging role in a collaborative dynamic environment. The right person will find many career growth opportunities in their company whether you want to advance your technical skills or aspire to leadership in the future.

Benefits:

• Flexible working hours
  (office open between 7 AM and 9 PM employees manage their own schedule)

• Hybrid working model

• One week per year work from anywhere

• 25 days annual leave plus December 24 and 31

• 150 per month food allowance ( 1800 per year additional compensation)

• Private medical insurance

• One time relocation bonus paid with the first salary

• Support with housing search through an agency

• Visa support if required

• Relocation support for family

• Virtual shares

• Language classes
  (Spanish English Catalan)

• Tax incentive