DFx verification
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Job Location:
Santa Clara County, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
3 hours ago
Vacancies:
1 Vacancy
Job Summary
DFx verification
No. of open positions- 05
Visa- H1B GCEAD GC or Citizens
Mode of work- Day 1 onsite
Interview Virtual
We have a priority requirement for DFx Verification. Currently we have 15 positions in Santa Clara and a resource with 4 years of experience would be ideal.
Key Responsibilities
Develop and execute verification plans for DFx features including:
Scan (stuck-at transition fault)
MBIST / LBIST
Boundary Scan (JTAG)
Memory repair and redundancy
Low-power test scenarios
Create and maintain testbenches using SystemVerilog/UVM for DFx validation
Verify:
Scan chain integrity and connectivity
Test mode functionality and coverage
ATPG pattern validation and debug
BIST controllers and memory test logic
Technical Skills
Scan (stuck-at transition fault)
MBIST / LBIST
Boundary Scan (JTAG)
Memory repair and redundancy
Low-power test scenarios
Create and maintain testbenches using SystemVerilog/UVM for DFx validation
Verify:
Scan chain integrity and connectivity
Test mode functionality and coverage
ATPG pattern validation and debug
BIST controllers and memory test logic
Technical Skills
Strong knowledge of:
DFT concepts (Scan ATPG MBIST JTAG)
Digital design fundamentals
Expertise in:
SystemVerilog and UVM
Simulation tools (VCS Xcelium Questa)
Familiarity with:
ATPG tools (TetraMAX Modus FastScan)
Debug tools (Verdi DVE)
Understanding of:
Low-power design (UPF/CPF)
Clocking and reset strategies
DFT concepts (Scan ATPG MBIST JTAG)
Digital design fundamentals
Expertise in:
SystemVerilog and UVM
Simulation tools (VCS Xcelium Questa)
Familiarity with:
ATPG tools (TetraMAX Modus FastScan)
Debug tools (Verdi DVE)
Understanding of:
Low-power design (UPF/CPF)
Clocking and reset strategies
