ASIC Physical Design Engineer

About the Position

We are looking to hire an ASIC Physical Design Engineer to help us design test and deploy advanced hardware. As part of our Ultra Low Latency team youll have the opportunity to collaborate with people in areas across the firm including trading networking and research infrastructure.

This isnt a traditional PD role. Were a small team where everyone works across the chip design process and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary.

If youve spent your career exclusively in PD this probably isnt the right fitbut if youve worked across the stack either because you started as an RTL designer and moved into PD or because you were on a smaller team where you had to wear multiple hats wed love to talk.

Were big believers in the ability of tools to improve the productivity reliability and day-to-day joy of hardware engineering. Thats why we created Hardcaml a hardware development toolchain embedded in OCaml. We dont expect you to know OCaml (well teach you here) but we are looking for hardware engineers who are excited about the advantages that better tools can bring and are willing to try new things as a result.

About You

• You have hands-on experience building and running modern physical design flows (e.g. floorplanning place and route timing closure physical verification power analysis)
• You dont need to have optimised every last detail of every flow but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
• Beyond PD you can read and write RTL and understand how front-end design decisions affect physical implementationand vice versa; You think about physical design in the context of the overall chip not just as a downstream consumer of a netlist
• Youre interested in using software engineering techniques to improve the hardware design process and you have experience programming in a high-level language (Python C Haskell etc.)
• Fluent in English

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