DMTS NOC Cache Coherency Architect

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design development and fabrication services to some of the worlds most inspired technology companies. With a global manufacturing footprint spanning three continents GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information visit .

Summary of Role:

MIPS - A GlobalFoundries company is seeking a highly experienced NOC and Cache Coherency Architect with over 15 years of industry experience to lead design efforts focused specifically on NOC Coherency Manager and Cache Controller components.

The successful candidate will have extensive hands-on experience utilizing advanced design methodologies. This senior role involves close collaboration with CPU core architects designers and cross-functional global teams to ensure high-quality high-performance processor designs.

Essential Responsibilities:
Lead and drive architectural specification and design activities for Coherency Manager and Cache Controller IP to closure.
Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
Automate and optimize verification flows and regression environments using scripting languages like Python Perl TCL or Shell.
Mentor design engineers providing technical guidance and leadership within the verification team.

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs.

Required Qualifications:
Masters degree or higher in Electronics/Electrical/Computer Engineering.
15 years of relevant verification experience specifically in CPU or complex SoC verification.
Proven expertise in Multicore and Multicluster Coherency Cache Controllers or similar blocks.
Proficiency in SystemVerilog Verilog C/C and Assembly.
Solid understanding of interconnect and coherency protocols such as AXI ACE OCP CHI.
Strong scripting skills in Python Perl TCL or Shell.
Experience with CPU architectures particularly RISC-V ARM or MIPS.

Preferred Qualifications:

Experience with RISC-V architecture.
Familiarity with functional safety standards (e.g. ISO 26262).
Prior exposure to FPGA prototyping and emulation platforms.
What MIPS Offers:
Opportunity to be part of a dynamic team creating industry-leading RISC-V processors.
Autonomy with extensive support from industry experts.
Opportunities for significant career growth and technical advancement.
Competitive compensation and comprehensive benefits package

Expected Salary Range

The exact Salary will be determined based on qualifications experience and location.