Senior Principal Software Engineer Accelerated Verification IP

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

The AVIP (Accelerated Verification IP) and Virtual Bridge (VB) business is a core part of Cadences Virtual Emulation and System Verification portfolio enabling highperformance verification on Palladium and Protium platforms. The team builds highperformance protocol solutions that enable customers to verify complex SoCs and systems at much higher speed and scale than traditional simulation.

Together AVIP and VB are critical to customers building highperformance compute AI networking and memorycoherent systems where early software bringup performance analysis and protocol compliance are essential.

The AVIP / Virtual Bridge R&D team designs implements and productizes protocol solutions that span hardware software and systemlevel verification. The team works across multiple layers including:

• Protocol architecture and feature definition
• Highperformance transactor and BFM development
• Hardwaresoftware cosimulation and emulation flows
• Debug logging performance profiling and compliance features
• Customer enablement escalations and interoperability validation

The team supports a broad portfolio of industrystandard protocols such as PCIe CXL Ethernet USB UCIe and emerging interconnects and works closely with emulation platform teams controller/PHY teams and customers.

This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products focusing on protocol functionality performance and robustness. Depending on the specific protocol area the work may involve:

• Implementing PCIe protocol features and state machines
• Enhancing performance and scalability on emulation platforms
• Developing debug trace and analysis capabilities
• Supporting systemlevel and softwaredriven use cases via PCIe Virtual Bridge
• Working with customers and field teams to resolve issues and deliver solutions related to PCIe and CXL

In this role the engineer will be responsible for designing developing and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution. The role is handson and spans feature development validation and customer readiness.

Key responsibilities include:

• Designing and implementing protocol functionality in PCIe AVIP and/or Virtual Bridge components
• Developing and debugging BFMs transactors and associated software interfaces
• Ensuring correctness performance and scalability in emulation and acceleration flows
• Collaborating with crossfunctional teams
• Participating in feature bringup regression and release activities
• Supporting customer issues reproducing problems and delivering fixes

What youll need

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Strong fundamentals in digital design computer architecture and systemlevel verification
• Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C
• Understanding of standard interconnect or IO protocols (e.g. PCIe CXL NVMe)
• Familiarity with emulation acceleration or hybrid verification flows is a strong plus
• Good debugging skills using waveforms logs and protocol analyzers
• Ability to work across hardware and software boundaries

The annual salary range for California is $154000 to $286000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

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