ASICFPGA Design and Verification Engineer (Lead, Senior, or Principal)

Company:

Boeing Space Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Design or Verification Engineers (Lead Senior or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeings products; ASICs and FPGAs in Albuquerque NM.

From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes the Boeing Electronic Products group develops ASICs and FPGAs that are at the heart of Boeings products.

We leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust high-performance custom processors using the latest ARM IP to enable high-integrity low SWAP-C flight computers. And were applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing.

Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line approximately half our design work is within the Space & Launch business unit and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike Surveillance and Mobility; and Autonomous Systems).

As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. This is a unique time where were hiring design and verification engineers at every level as were only limited by our bandwidth for new projects. We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics that we build in El Segundo or for units designed at other sites.

Within the LEOS team you will be working with high-performance laser gimbal control systems. Responsibilities encompass the design and development of FPGA designs and their embedded software. Youll work with cross-functional teams including hardware and software engineers to define/refine system requirements specifications and ensure seamless software-hardware compatibility.

Specific responsibilities include:

- Conduct unit-level testing verification and validation of embedded software and firmware utilizing debugging tools like oscilloscopes and logic analyzers to identify and resolve issues.

- Create and maintain technical documentation including requirements documents design specifications test plans and interface control documents.

- Support the integration of software and hardware components from initial hardware bring-up to final system validation.

- Analyze and enhance the efficiency stability scalability and performance of system resources often within the constraints of low power or memory.

Position Responsibilities:

• Lead FPGA/ASIC designs including multi-FPGA/ASIC programs and teams with design and verification engineers and manage team execution to meet program milestones

• Collaborate with customers system engineers and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs

• Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts weighing Schedule Cost Risk Area Power (SCRAP) vs. performance

• Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture through HDL coding and physical design realization (through gate-level netlists for ASIC designs)

• Integrate DSP IP from Boeings algorithm team and third-party IP as needed

• Perform static timing analysis LEC CDC linting and other necessary checks to ensure the design is completed on schedule

• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation

• Create self-checking and reusable test benches from scratch applying Object Oriented Programming concepts such as Inheritance and Polymorphism and leverage UVM to create drivers monitors predictors and scoreboards

• Drive FPGA-based prototyping and validation depending on program and system requirements and complexity

• Validate design through hardware integration test with special test equipment test-beds and higher-level systems as needed

• Train and mentor less senior engineers across the department and help build effective project teams

This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.

Basic Qualifications (Required Skills/Experience):

• Bachelor of Science degree in Engineering (with a focus in Electrical Mechanical or Aeronautical) Computer Science Data Science Mathematics Physics Chemistry or non-US equivalent qualifications directly related to the work statement

• 9 years of ASIC/FPGA design or verification experience (or minimum Masters and 7 years of ASIC/FPGA design or verification experience)

• Experience with ASIC/FPGA architectural definition and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs

• Professional experience with hardware-based integration and test of ASIC/FPGA designs

Preferred Qualifications (Desired Skills/Experience):

• Senior Level 5: 14 years of related work experience or an equivalent combination of education and experience

• Principal Level 6: 20 years of related work experience or an equivalent combination of education and experience

• Masters Degree in EE Computer Engineering/Science or related field or equivalent experience

• Proven record of leading ASIC/FPGA design and/or verification teams including tracking and reporting progress to stakeholders

• Experience with hardware emulators especially Palladium

• Proficiency with hardware verification languages: System Verilog System Verilog Assertions

• Ability to executable test plans

• Proficiency with Object Oriented Programming Concepts: Inheritance Polymorphism etc.

• Ability to create self-checking and reusable testbenches from scratch

• Experience developing Functional Coverage Models and Closing Code Coverage

• Experience with high-speed Serdes interfaces (JESD204C PCIe Ethernet)

• Proficient in scripting languages: Make Perl Python etc.

• Revision Control Systems: svn cvs git

• Proficient in Linux Environments

• Familiarity with space-based design techniques and radiation mitigation

• Demonstrated history of 1st pass success with ASIC designs

Conflict of Interest:

Successful candidate for this job must satisfy the Companys Conflict of Interest (COI) assessment process.

Typical Education/Experience:

Lead (Level 4):

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 9 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Senior (Level 5):

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 14 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Principal (Level 6):

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 20 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard

Relocation:

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace:

Boeingis a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana cocaine opioids amphetamines PCP and alcohol when criteria is met as outlined in our policies.

Shift Work Statement:

This position is for 1st shift.

At Boeing we strive to deliver a Total Rewards package that will attract engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs generally including health insurance flexible spending accounts health savings accounts retirement savings plans life and disability insurance programs and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location date of hire and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications as well as market and business considerations.

Summary pay range for Lead (Level 4): $136850 - $185150

Summary pay range for Senior (Level 5): $164900 - $223100

Summary pay range for Principal (Level 6): $197200 - $266800

Language Requirements:

Education:

Relocation:

Export Control Requirement:

Safety Sensitive:

Security Clearance:

Visa Sponsorship:

Contingent Upon Award Program

Shift:

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