Principal Design Verification Engineer

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design development and fabrication services to some of the worlds most inspired technology companies. With a global manufacturing footprint spanning three continents GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information visit .

Summary of Role:

MIPS A GlobalFoundries company is seeking a Design Verification Engineer with 8 years of experience to join our CPU verification team. The successful candidate will work on verification of processor components focusing on CPU core functionality coherency and cache subsystems. This role offers an excellent opportunity to gain hands-on experience with advanced verification methodologies and collaborate with world-class architects and designers.

Essential Responsibilities:

• Perform functional verification of CPU cores and related subsystems (coherency and cache controllers).
• Understand and interpret microarchitectural specifications to develop effective verification strategies.
• Develop and execute verification plans including testbench creation and test case development.
• Write directed and constrained random test cases in SystemVerilog C and Assembly.
• Utilize UVM-based environments for coverage-driven verification.
• Analyze coverage reports and assist in closing coverage gaps.
• Automate regression and verification flows using scripting languages such as Python Perl or Shell.
• Collaborate with senior engineers and architects to ensure design quality and performance.

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs.

Required Qualifications:

• Bachelors degree in Electronics/Electrical/Computer Engineering.
• 8 years of experience in design verification preferably in CPU or SoC verification.
• Hands-on experience with SystemVerilog UVM and constrained random verification.
• Familiarity with CPU architectures such as RISC-V ARM or MIPS.
• Basic understanding of cache and coherency concepts.
• Strong scripting skills in Python Perl or Shell.

Preferred Qualifications :

• Exposure to RISC-V architecture.
• Knowledge of interconnect protocols like AXI ACE or CHI.
• Experience with FPGA prototyping or emulation platforms.

Expected Salary Range

The exact Salary will be determined based on qualifications experience and location.