Senior Physical Design Engineer 135hr

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco our investors include Benchmark General Catalyst Peter Thiel Adam DAngelo Larry Summers and Jack Dorsey.

Position: ASIC Power Engineer
Type: Contract
Compensation: $100$135/hour
Location: United States

Role Responsibilities

• Perform PPA optimization with Fusion compiler to enhance ASIC efficiency.
• Conduct RTL and netlist level power analysis to improve power management.
• Execute post-processing and scripting on report log files for format conversion and data analysis.
• Setup run debug and analyze reports of ASIC flows including Synthesis PD Power and Timing.
• Implement blocks at RTL and UPF to optimize design processes.
• Document and communicate findings clearly to enhance team understanding.

Qualifications

Must-Have

• 10 years of experience as an ASIC Power Engineer or CAD/Physical Design Engineer.
• Experience with power estimation tools and synthesis including some physical design.
• Knowledge of power trade-offs in design and back end implementation.
• Hands-on experience in scripting and data analysis.
• Bachelors degree in Electrical Engineering/Computer Science or equivalent experience.

Preferred

• Experience with Synopsys (DC ICC PTPX/PrimePower VCS Verdi) and/or Cadence (Joules).
• Python Perl (or similar) scripting and data-post-processing tools.
• Excel (or Matlab) for model fitting data visualization and analysis.
• Experience in low power design tools and methodologies including power intent UPF specifications.
• Silicon Power Characterization.
• Some power profiling experience at IP/SoC level.

Application Process (Takes 2030 mins to complete)

• Upload resume
• AI interview based on your resume
• Submit form

Resources & Support

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PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.