Sr. Memory & Storage Architect

Position Overview

The Sr. Memory & Storage Architect will own detailed design of the tiered CXL 3.1class memory subsystem that underpins the next-generation key-value platform. This role defines memory pool architectures designs Near-Data Processing logic for in-memory KV-cache operations and partners with system software engineers to expose these capabilities through extended inference runtimes.

Key Responsibilities

Design CXL 3.1generation Type-2 and Type-3 tiered memory pool architectures supporting hot KV-cache in high-bandwidth memory and cold KV offloaded to DDR5 via intelligent tiering logic.

Architect Near-Data Processing (NDP) engines co-located with CXL memory for attention score computation KV compression/decompression and vector operations to minimize CPU round-trips.

Define memory controller microarchitecture including arbitration policy prefetching strategies ECC and inline encryption for KV-cache at rest.

Build detailed memory subsystem performance models and validate against LLM inference benchmarks (e.g. TTFT throughput memory utilization).

Partner with system software teams to surface NDP capabilities via and define software interfaces for block-level KV-cache offloading.

Evaluate DDR5 DIMM and CXL memory expander vendors; define qualification criteria and design-in requirements.

Develop storage-class memory integration strategies for long-term context persistence beyond DRAM capacity limits.

Contribute to IP filings for novel memory architecture innovations.

Required Skills & Experience

10 years in memory subsystem architecture with deep DDR5/LPDDR5x expertise and at least one CXL-based product or research prototype.

Expert-level knowledge of CXL 2.0/3.0/3.1 specifications: device models / / protocols fabric switching and coherency semantics.

Demonstrated NDP or PIM design experience (or equivalent academic/industry research on processing-near-memory architectures).

Strong analytical ability to build cycle-accurate or analytical memory models and correlate them with silicon measurements.

Familiarity with LLM inference memory access patterns including KV-cache management and modern attention/paging techniques.

Proficiency with EDA tools for verification of memory IP blocks and RTL-level understanding of memory controller design.

Preferred Qualifications

Prior experience at leading memory vendors or companies in the CXL ecosystem.

Publications or patents in NDP PIM or disaggregated memory architecture.

Understanding of open-source memory simulation tools (such as DRAMsim3 or Ramulator) and emerging interconnect standards for memory-centric systems.