Power Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology revolutionizing performance expectations ease of use and cost efficiency. With AI redefining the computing paradigm solutions must evolve to unify innovations in software models compilers platforms networking and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration curiosity and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a person ready to take up the challenge of working in a high-profile projectwhere we design and integrate multiple chiplets into a System-in-package in collaboration withexternal stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USAJapan and other countries and help us make our IP even is a CPU tech-leadership role focused on driving power analysis and projections for thedevelopment of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities includeoptimizing the system PDN for Block rails and managing the power vector plan for comprehensivecoverage of Chip level. The position requires driving power analysis on RTL and Netlist using toolslike Joules and PrimePower working with RTL design synthesis and physical design teams tomeasure and optimize power and evaluating new power optimization techniques at various designstages. Additionally the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements.

This role ishybrid based out of Tokyo Japan

We welcome candidates at various experience levels for this role. During the interview process candidates will be assessed for the appropriate level and offers will align with that level which may differ from the one in this posting.

Who You Are

• Extensive experience in power analysis and optimization for complex ASICs (typically 10 years of ASIC or related design experience).
• Comfortable working across RTL synthesis and physical design stages including lowpower implementation techniques and ECObased timing closure.
• Proficient with power analysis tools (e.g. Joules PrimePower) and scripting (Tcl plus at least one of Python or similar).
• Strong analytical and problemsolving skills with clear written and verbal communication when collaborating across SoC board and postsilicon teams.
• Nice to have: familiarity with UPF/CPF lowpower intent Verilog/SystemVerilog CPU microarchitecture and its power challenges and basic thermal analysis.

What We Need

• Own power analysis and projections for the CPU chiplet with emphasis on defining and tracking power metrics throughout the design cycle.
• Define and maintain the power vector plan for comprehensive chipletlevel and chiplevel coverage.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower partnering with RTL design synthesis and physical design teams to measure and optimize power.
• Evaluate and propose new power optimization techniques at RTL synthesis and physical design stages and implement changes via timing ECO and flow updates.
• Tabulate and compare power metrics and reports across design iterations and work with postsilicon teams to correlate projections with silicon measurements.

What You Will Learn

• How to define and execute a power strategy for a 2nm CPU chiplet within a multichiplet systeminpackage including rail planning and systemlevel PDN optimization.
• Best practices for endtoend power closure from RTL through netlist and physical design in collaboration with global RTL SoC and board teams.
• How to correlate presilicon power models with real silicon behavior and feed lessons learned back into nextgeneration CPU and SiP architectures.
• How Tenstorrent integrates CPU chiplets AI accelerators and boardlevel power delivery into a cohesive highperformance platform.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws including those codified in the U.S. Export Administration Regulations (EAR) the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1 E1 and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information systems or technologies subject to these laws the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws any offer of employment will be rescinded.