Description:
The selected candidate will be responsible for ASIC & FPGA design on R&D program.
Requirements :
- Active Secret Clearance
- FPGA Design
- DSP/Radio
Preferred skills:
Responsibilities:
- Cross discipline collaboration with RTL Designers Systems Architects RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth contributing to complex systems employing high speed networking concepts.
- The selected candidate will also provide support and technical direction to junior engineers.
- Overall contribution to simulation verification integration & test of complex high speed products
Description: The selected candidate will be responsible for ASIC & FPGA design on R&D program. Requirements : Active Secret Clearance FPGA Design DSP/Radio Preferred skills: Spyglass Responsibilities: Cross discipline collaboration with RTL Designers Systems Architects RF/Analog & Digital Circ...
Description:
The selected candidate will be responsible for ASIC & FPGA design on R&D program.
Requirements :
- Active Secret Clearance
- FPGA Design
- DSP/Radio
Preferred skills:
Responsibilities:
- Cross discipline collaboration with RTL Designers Systems Architects RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth contributing to complex systems employing high speed networking concepts.
- The selected candidate will also provide support and technical direction to junior engineers.
- Overall contribution to simulation verification integration & test of complex high speed products
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