Senior Distinguished Engineer, Architecture ASIC System

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

As a Senior Distinguished SoC architect youll be responsible for:

• Engaging with customers engineering and marketing to lead chip architecture of innovative and complex processor-based SoCs
• Specifying product requirements and driving to closure
• Architecting new blocks and capabilities
• Overseeing and coordinating IP evaluation IP block microarchitecture pinouts cost estimates and power estimates
• Communicating and coordinating with other business units in Marvell on internal IP and sharing capabilities and knowledge
• Presenting trainings to peers helping develop the team and mentoring other architects/engineers

What Were Looking For

Required qualifications:

• A degree in Electrical/Computer Engineering or Computer Science or related fields.
• A minimum of 20 years of experience in system architecture development and related fields
• Demonstrated expertise in SoC architecture e.g. interconnects I/O technologies virtualization memory hierarchies clocks resets power management security etc.
• Demonstrated technical leadership delivering complex silicon solutions.

Preferred qualifications:

• Knowledge of modern networking protocols
• Experience with heterogenous SoCs and NoC interconnects
• Knowledge of Arm v8/v9 processors and Arm CHI and AXI interconnects
• Knowledge of RISC-V processors and related systems
• Deep understanding of ASIC design flow including RTL design verification with SystemVerilog logic synthesis place and route timing closure etc.
• Ability to present to customers and collect and analyze customer feedback
• Experience working with geographically distributed teams

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.